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    A semiconductor memory system
    72.
    发明公开
    A semiconductor memory system 有权
    Halbleiterspeichersystem

    公开(公告)号：EP1262995A1

    公开(公告)日：2002-12-04

    申请号：EP01830345.3

    申请日：2001-05-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi

    IPC: G11C16/04 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C16/0475 ,  G11C16/0491

    Abstract: A memory system (1000) comprises a memory matrix (110) formed on a semiconductor structure, the memory matrix including:

    a first column line (BC-4) and a second column line (BC-5) which are connected electrically to at least one first memory cell (Q 65 ) to be read, for the reading of the at least one first cell (Q 65 ) a first reading voltage can be supplied to the first column line (BC-4), and
    a third column line (BC-1) distinct from the first column line (BC-4) and from the second column line (BC-5), and is characterized in that it further comprises generating means (SCR) for supplying, to the third column line (BC-1) and during the reading of the at least one first memory cell (Q 65 ), a biasing voltage which can oppose the establishment of an electric current between the first column line (BC-4) and the third column line (BC-1) in the semiconductor structure. The biasing voltage is preferably substantially equal to the first reading voltage.

    Abstract translation: 存储系统（1000）包括形成在半导体结构上的存储矩阵（110），所述存储矩阵包括：至少与第一列线（BC-4）和第二列线（BC-5）电连接的第一列线 要读取的第一存储单元（Q65），为了读取至少一个第一单元（Q65），第一列线（BC-4）可以提供第一读取电压，第三列线（BC- 1）与第一列线（BC-4）和第二列线（BC-5）不同，其特征在于还包括产生装置（SCR），用于向第三列线（BC-1） ）并且在读取至少一个第一存储单元（Q65）期间，可以在第一列线（BC-4）和第三列线（BC-1）之间建立电流的偏置电压 半导体结构。 偏置电压优选地基本上等于第一读取电压。

    Interlaced memory device with random or sequential access
    74.
    发明公开
    Interlaced memory device with random or sequential access 有权
    Verschachtelte Speichereinrichtung mitwillkürlichemund sequentiellem Zugriff

    公开(公告)号：EP1199723A1

    公开(公告)日：2002-04-24

    申请号：EP00830675.5

    申请日：2000-10-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tomaiuolo, Francesco ,  Nicosia, Salvatore ,  Pascucci, Luigi

    IPC: G11C7/10 ,  G11C8/00

    CPC classification number: G11C7/1033 ,  G11C7/1045

    Abstract: A new multipurpose interlaced memory device functions in two different modes: synchronous and asynchronous, using a circuit for detecting address transitions that by acting as a synchronous clock of the system lets the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of cells.
    The memory device has a buffer for outputting a datum provided with means that for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.

    Abstract translation: 新的多用途隔行存储器件以两种不同的模式工作：同步和异步，使用用于检测地址转换的电路，通过充当系统的同步时钟，使存储器件的控制电路通过启用比较来识别所需的访问模式 当前输入的外部地址与存储在两组单元格的地址计数器中的一个相同。 存储器件具有用于输出提供有用于将输出节点预充电到对应于两个可能的逻辑状态的电压之间的中间电压的装置的基准的缓冲器，从而减少噪声并改善传输时间。

    Method for reading a memory, particularly a non-volatile memory
    78.
    发明公开
    Method for reading a memory, particularly a non-volatile memory 有权
    Verfahren zum Lesen eines Speichers，insbesondere einesnichtflüchtigenSpeichers

    公开(公告)号：EP1017059A1

    公开(公告)日：2000-07-05

    申请号：EP98830801.1

    申请日：1998-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi ,  Fontana, Marco

    IPC: G11C7/00

    CPC classification number: G11C7/1018

    Abstract: A method for reading a memory, particularly a non-volatile memory, whose particularity is that it comprises the steps of:

    generating a memory enable signal (CE);
    generating a signal (ALE) for the visibility, inside the memory, of address signals generated externally with respect to the memory, the address signals being adapted to allow access to corresponding memory locations of the memory;
    generating a signal (RD) for the synchronous advancement of the read operation within the memory;
    each change of state of the memory enable signal (CE), together with a change of state of the address signals, being matched by different cycles for reading the memory, the different read cycles being enabled according to the state of the signal (ALE) for the visibility, inside the memory, of address signals generated externally to the memory, the logic state of the visibility signal switching between the high logic state, the low logic state and the pulsed state; emission of the data read from the memory being correlated to the state transition of the signal (RD) for the synchronous advancement of the reading of the memory.

    Abstract translation: 一种用于读取存储器，特别是非易失性存储器的方法，其特征在于其包括以下步骤：产生存储器使能信号（CE）; 产生用于在存储器内的对于存储器在外部产生的地址信号的可见性的信号（ALE），所述地址信号适于允许访问存储器的相应存储器位置; 产生用于在存储器内同步提前读取操作的信号（RD）; 存储器使能信号（CE）的状态的每个改变与地址信号的状态的改变一起被用于读取存储器的不同周期匹配，根据信号（ALE）的状态启用不同的读取周期， 为了存储器内部可见的内部存储器中产生的地址信号的可见性，可视信号的逻辑状态在高逻辑状态，低逻辑状态和脉冲状态之间切换; 从存储器读取的数据的发射与用于对存储器的读取的同步提前的信号（RD）的状态转换相关。

    Method and system for refreshing a memory device during reading thereof
    80.
    发明公开
    Method and system for refreshing a memory device during reading thereof 审中-公开
    一种用于他们的阅读期间更新存储器件的方法和系统

    公开(公告)号：EP1843356A1

    公开(公告)日：2007-10-10

    申请号：EP06112157.0

    申请日：2006-04-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rolandi, Paolo ,  Pascucci, Luigi

    IPC: G11C11/56 ,  G11C16/34

    CPC classification number: G11C16/3431 ,  G11C11/5628 ,  G11C16/3418

    Abstract: A refresh circuit (130) for refreshing a memory device (100) is proposed. The refresh circuit includes: reading means (110-125,505m,505r i ,515-520) for reading a set of memory cells (MC), the reading means including means (110-125) for applying a biasing voltage having a substantially monotone time pattern to the memory cells and to a set of reference cells (RC) each one having a predefined reference threshold voltage, means (505m,505r i ) for reading the stored state of a certain memory cell by detecting the reaching of a comparison current (Ic) by a cell current (Im) of each memory cell and by a reference current (Ir i ) of each reference cell, and means (515-520) for determining a refresh condition of said memory cell by again reading the stored state at a later time, and writing means (555) for applying a writing voltage to said memory cell; the refresh circuit further includes control means (505g i ,525-550;525',705,530-550) for enabling the writing means during at least part of the application of the biasing voltage after the determination that said cell is in the refresh condition.

    Abstract translation: 用于刷新的存储器装置（100）的刷新电路（130）被提议。 所述刷新电路包括：用于读出一组存储器单元（MC）的读取装置（110-125,505m，505R I，515-520），读出装置包括用于（110-125），用于将基本上具有单调的偏置电压 时间图案到存储单元以及一组参考单元（RC）每一个具有预定的基准阈值电压的装置（505米，505R i）用于通过检测的比较电流的到达读取某存储单元的所存储的状态 每个参考单元（Ic）中由一个单元电流的每个存储单元的（IM）和由参考电流（IR i）中，以及装置（515-520），用于确定性采矿通过再次读出存储的状态中，所述存储单元的刷新条件 在稍后的时间，和用于施加写入电压给所述存储器单元写入装置（555）; 所述刷新电路包括另一控制设备（505克I，525-550; 525”，705.530-550）用于使写入的偏置电压的所述细胞是在刷新条件的判断后的应用程序的至少一部分期间的装置。

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