公开(公告)号：US20230207647A1

公开(公告)日：2023-06-29

申请号：US18115780

申请日：2023-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Ming-Chi Li ,  Chih-Mou Lin ,  Yu-Hsiang Hung ,  Yu-Hsiang Lin ,  Tzu-Lang Shih

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L29/0607 ,  H01L29/66545 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/6656 ,  H01L29/7833

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

公开(公告)号：US20220376071A1

公开(公告)日：2022-11-24

申请号：US17369985

申请日：2021-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Ming-Chi Li ,  Chih-Mou Lin ,  Yu-Hsiang Hung ,  Yu-Hsiang Lin ,  Tzu-Lang Shih

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

公开(公告)号：US10978457B2

公开(公告)日：2021-04-13

申请号：US16177413

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Yu-Hsiang Hung ,  Ming-Te Wei

IPC: H01L27/108 ,  H01L23/532

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width X1 and a width X2. The width X1 is aligned with the top portion of the rounding hard mask in a horizontal direction, and the width X2 is aligned with the bottom portion of the rounding hard mask in the horizontal direction, X1 is greater than or equal to X2.

公开(公告)号：US10978398B2

公开(公告)日：2021-04-13

申请号：US16732336

申请日：2020-01-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78 ,  H01L23/485

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.

公开(公告)号：US10529856B2

公开(公告)日：2020-01-07

申请号：US16028187

申请日：2018-07-05

Applicant: United Microelectronics Corp.

Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308

Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

公开(公告)号：US10062604B2

公开(公告)日：2018-08-28

申请号：US15643488

申请日：2017-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/485

CPC classification number: H01L21/7682 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28132 ,  H01L21/28141 ,  H01L21/2815 ,  H01L21/28247 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823864 ,  H01L21/845 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66689 ,  H01L29/66719

Abstract: A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.

公开(公告)号：US10050146B2

公开(公告)日：2018-08-14

申请号：US14462114

申请日：2014-08-18

Applicant: United Microelectronics Corp.

Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308

Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

公开(公告)号：US20180138088A1

公开(公告)日：2018-05-17

申请号：US15871037

申请日：2018-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/535 ,  H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/033 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7851

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.

公开(公告)号：US20180012976A1

公开(公告)日：2018-01-11

申请号：US15695019

申请日：2017-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.

公开(公告)号：US20170323852A1

公开(公告)日：2017-11-09

申请号：US15170954

申请日：2016-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L23/535 ,  H01L29/267 ,  H01L29/24 ,  H01L29/165 ,  H01L29/161 ,  H01L29/08 ,  H01L23/528 ,  H01L21/768 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.