公开(公告)号：EP3408938A1

公开(公告)日：2018-12-05

申请号：EP16816469.7

申请日：2016-11-16

Applicant: Xilinx, Inc.

Inventor： HEARNE, Catherine ,  UPADHYAYA, Parag ,  GEARY, Kevin

IPC: H03K5/135 ,  H03K5/00

CPC classification number: H03K5/135 ,  H03K2005/00052 ,  H03K2005/00058

Abstract: A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.

公开(公告)号：EP3289687A1

公开(公告)日：2018-03-07

申请号：EP16723574.6

申请日：2016-04-26

Applicant: Xilinx, Inc.

Inventor： UPADHYAYA, Parag ,  BEKELE, Adebabay, M. ,  TURKER MELEK, Didem, Z. ,  WU, Zhaoyin, D.

IPC: H03L7/18 ,  H03L7/197

Abstract: In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.

公开(公告)号：EP3235122A1

公开(公告)日：2017-10-25

申请号：EP15798642.3

申请日：2015-11-12

Applicant: Xilinx, Inc.

Inventor： BEKELE, Adebabay, M. ,  UPADHYAYA, Parag

IPC: H03B5/12

CPC classification number: H03B5/1253 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1271 ,  H03B5/1278 ,  H03B5/129 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03B2201/0291 ,  H03B2201/031 ,  H03B2201/038

Abstract: Voltage-controlled oscillation (100) is described. In an apparatus therefor, an inductor (120) has a tap and has or is coupled to a positive-side output node (105) and a negative side output node (106). The tap is coupled to receive a first current. A coarse grain capacitor array (130) is coupled to the positive-side output node (105) and the negative side output node (106) and is coupled to respectively receive select signals (168). A varactor (140) is coupled to the positive-side output node (105) and the negative side output node (106) and is coupled to receive a control voltage (143). The varactor (140) includes MuGFETs (141, 142). A transconductance cell (150) is coupled to the positive- side output node (105) and the negative side output node (106), and the transconductance cell (150) has a common node (107). A frequency scaled resistor network (160) is coupled to the common node (107) and is coupled to receive the select signals (168) for a resistance for a path for a second current.

Abstract translation: 描述电压控制振荡（100）。 在其设备中，电感器（120）具有抽头并且具有或者耦合到正侧输出节点（105）和负侧输出节点（106）。 抽头被耦合以接收第一电流。 粗粒度电容器阵列（130）耦合到正侧输出节点（105）和负侧输出节点（106）并且被耦合以分别接收选择信号（168）。 变容二极管（140）耦合到正侧输出节点（105）和负侧输出节点（106）并且被耦合以接收控制电压（143）。 变容二极管（140）包括MuGFET（141,142）。 跨导单元（150）耦合到正侧输出节点（105）和负侧输出节点（106），并且跨导单元（150）具有公共节点（107）。 频率调节电阻网络（160）耦合到公共节点（107）并且被耦合以接收用于第二电流的路径的电阻的选择信号（168）。

公开(公告)号：EP2628164B1

公开(公告)日：2016-06-08

申请号：EP11760636.8

申请日：2011-09-12

Applicant: Xilinx, Inc.

Inventor： KIREEV, Vassili ,  UPADHYAYA, Parag ,  MARLETT, Mark, J.

IPC: H01F17/00

CPC classification number: H01F17/0013 ,  H01F2017/0073 ,  Y10T29/4902

公开(公告)号：EP2628241A1

公开(公告)日：2013-08-21

申请号：EP11754596.2

申请日：2011-08-31

Applicant: Xilinx, Inc.

Inventor： UPADHYAYA, Parag ,  KIREEV, Vassili

IPC: H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/124 ,  H03B5/1262 ,  H03B5/1265 ,  H03B2201/02 ,  H03B2201/0208 ,  H03B2201/0266

Abstract: A tunable resonant circuit (102) includes first capacitors (104, 108, 216, 228, 232) and second capacitors (106, 1 10, 218, 230, 234) that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well (320, 326) disposed within a second well (322, 328) in a substrate (324). The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor (120, 130) are respectively coupled to the second electrode (1 14, 304) of the first capacitor and the second electrode (1 18, 308) of the second capacitor. Two channel electrodes of a second transistor (122, 132) are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor (124, 134) are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes (226, 314) of the first, second, and third transistors are responsive to a tuning signal (126, 136), and an inductor (144, 202) is coupled between the first electrodes (1 12, 1 16, 302, 306) of the first and second capacitors.