Abstract:
Embodiments of this application disclose a dual-mode oscillator and a multi-phase oscillator. In the dual-mode oscillator, switching between two operating modes is implemented by using a mode switching circuit, so that oscillation signals having two different bands can be obtained. Moreover, the dual-mode oscillator includes two transformer-coupled oscillators, and a step-up transformer in any transformer-coupled oscillator multiplies a drain voltage swing of a first MOS transistor and then injects a voltage signal to a gate of a second MOS transistor, so that a larger gate voltage swing is obtained without increasing a supply voltage of the oscillator, and phase noise performance of the dual-mode oscillator is improved. In the multi-phase oscillator, multiple dual-mode transformer-coupled oscillators are connected through multi-phase coupled circuits to form a Mobius loop, so that oscillation signals in multiple phases can be generated, and phase noise performance of the entire oscillator can be improved.
Abstract:
An oscillator circuit (100) has a reconfigurable oscillator amplifier (110, 400). The reconfigurable oscillator amplifier (110, 400) is used to be coupled to a resonant circuit (102, R2) in parallel. The reconfigurable oscillator amplifier (110, 400) supports different circuit configurations for different operation modes, respectively. The reconfigurable oscillator amplifier (110, 400) has at least one circuit component shared by the different circuit configurations. The reconfigurable oscillator amplifier (110, 400) employs one of the different circuit configurations under one of the different operation modes.
Abstract:
The invention relates to a radio frequency oscillator (100), the radio frequency oscillator (100) comprising a resonator circuit (101) being resonant at an excitation of the resonator circuit (101) in a differential mode and at an excitation of the resonator circuit (101) in a common mode, wherein the resonator circuit (101) has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit (101) has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit (103) being configured to excite the resonator circuit (101) in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit (105) being configured to excite the resonator circuit (101) in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.
Abstract:
An oscillator circuit may selectively switch between a normal mode and a low-power mode in response to a mode signal. During the normal mode, the oscillator circuit may employ a first amplifier configuration and a first capacitive loading to generate a high-accuracy clock signal having a relatively low frequency error. During the low power mode, the oscillator circuit may employ a second amplifier configuration and a second capacitive loading to generate a low-power clock signal using minimal power consumption. A compensation circuit may be used to offset a relatively high frequency error during the low-power mode.
Abstract:
An oscillator circuit having a source of an oscillating signal, a tank circuit including an inductor (18, 420, 421) and a capacitor (18, 420, 421), and a discretely switchable capacitance module (14, 314) configured to control an amount of capacitance in the oscillator circuit. The discretely switchable capacitance module (14, 314) includes, a capacitor (22, 322) coupled between a first node (41, 341) and a second node (42, 342), a switch (24, 320) coupled between the second node (42, 322) and a third node (43, 343); and a DC feed circuit (28, 328, 329), having a first end (28a, 328a, 329a) coupled to the second node (42) and a second end (28b, 328b, 329b) configured to receive a first or second control signal (30, 330). The control node (25, 325) of the switch (24, 320) is tied to a predetermined bias voltage (26, 326). When the first control signal (30, 330) is applied, the capacitor (22) is coupled between the first node (41, 341) and the third node (43, 343) via the switch (24, 320), and when the second control signal (30, 330) is applied the capacitor (22) is decoupled from the inductor (18, 420, 421).
Abstract:
A radio transmitter and/or receiver comprising: an oscillator tuning circuit comprising an adjustable capacitor whose capacitance is adjustable my means of a first tuning signal; a filter tuning circuit comprising an adjustable capacitor whose capacitance is adjustable by means of a second tuning signal; an oscillator whose operational frequency is dependant on the reactance of the oscillator tuning circuit; a filter for filtering signals in the course of transmission and/or reception, and whose response is dependant on the reactance of the filter tuning circuit; and a tuning unit for generating the first and second tuning signals; wherein at least a part of the filter tuning circuit is a replica of at least a part of the oscillator tuning circuit and the tuning circuit is capable of generating one of the first and second tuning signals in dependence on the other of the tuning signals.
Abstract:
In a phase-lock-loop circuit a frequency detector measures a frequency error between an oscillatory signal and a synchronizing signal in alternate horizontal line periods for generating a frequency error indicative signal. The frequency error indicative signal is applied to an oscillator for correcting the frequency error in other alternate horizontal line periods in a manner to prevent frequency error measurement and correction from occurring in the same horizontal line period.
Abstract:
A tunable resonant circuit (102) includes first capacitors (104, 108, 216, 228, 232) and second capacitors (106, 1 10, 218, 230, 234) that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well (320, 326) disposed within a second well (322, 328) in a substrate (324). The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor (120, 130) are respectively coupled to the second electrode (1 14, 304) of the first capacitor and the second electrode (1 18, 308) of the second capacitor. Two channel electrodes of a second transistor (122, 132) are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor (124, 134) are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes (226, 314) of the first, second, and third transistors are responsive to a tuning signal (126, 136), and an inductor (144, 202) is coupled between the first electrodes (1 12, 1 16, 302, 306) of the first and second capacitors.