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    TUNABLE RESONANT CIRCUIT IN AN INTEGRATED CIRCUIT
    1.
    发明申请
    TUNABLE RESONANT CIRCUIT IN AN INTEGRATED CIRCUIT 审中-公开
    集成电路中的可调谐谐振电路

    公开(公告)号：WO2012050676A1

    公开(公告)日：2012-04-19

    申请号：PCT/US2011/050048

    申请日：2011-08-31

    Applicant: XILINX. INC.

    Inventor： UPADHYAYA, Parag ,  KIREEV, Vassili

    IPC: H03B5/12

    CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/124 ,  H03B5/1262 ,  H03B5/1265 ,  H03B2201/02 ,  H03B2201/0208 ,  H03B2201/0266

    Abstract: A tunable resonant circuit (102) includes first capacitors (104, 108, 216, 228, 232) and second capacitors (106, 1 10, 218, 230, 234) that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well (320, 326) disposed within a second well (322, 328) in a substrate (324). The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor (120, 130) are respectively coupled to the second electrode (1 14, 304) of the first capacitor and the second electrode (1 18, 308) of the second capacitor. Two channel electrodes of a second transistor (122, 132) are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor (124, 134) are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes (226, 314) of the first, second, and third transistors are responsive to a tuning signal (126, 136), and an inductor (144, 202) is coupled between the first electrodes (1 12, 1 16, 302, 306) of the first and second capacitors.

    Abstract translation: 可调谐谐振电路（102）包括在第一和第二电极之间提供匹配电容的第一电容器（104,108,216,228,232）和第二电容器（106,110,218,230,234） 第二电容器。 深井布置包括设置在衬底（324）中的第二阱（322,328）内的第一阱（320,326）。 第一和第二电容器各自设置在第一阱上。 第一晶体管（120,130）的两沟道电极分别耦合到第一电容器的第二电极（114）和第二电容器的第二电极（118,188）。 第二晶体管（122,132）的两沟道电极分别耦合到第一电容器的第二电极并接地。 第三晶体管（124,134）的两沟道电极分别耦合到第二电容器的第二电极并接地。 第一，第二和第三晶体管的栅极电极（226,314）对调谐信号（126,136）作出响应，并且电感器（144,202）耦合在第一电极（112,126， 302,306）的第一和第二电容器。

    DIGITAL FRACTIONAL-N MULTIPLYING INJECTION LOCKED OSCILLATOR
    5.
    发明公开
    DIGITAL FRACTIONAL-N MULTIPLYING INJECTION LOCKED OSCILLATOR 审中-公开

    公开(公告)号：EP3440774A1

    公开(公告)日：2019-02-13

    申请号：EP17718759.8

    申请日：2017-04-06

    Applicant: Xilinx, Inc.

    Inventor： NANDWANA, Romesh K. ,  UPADHYAYA, Parag

    IPC: H03L7/08 ,  H03L7/099

    CPC classification number: H03L7/24 ,  H03L7/0805 ,  H03L7/081 ,  H03L2207/06 ,  H03L2207/50

    Abstract: An example clock generator circuit includes a fractional reference generator configured to generate a reference clock in response to a base reference clock and a phase error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock. The clock generator circuit includes a digitally controlled delay line (DCDL) that delays the reference clock based on a first control code, and a pulse generator configured to generate pulses based on the delayed reference clock. The clock generator circuit includes a digitally controlled oscillator (DCO) configured to generate an output clock based on a second control code, the DCO including an injection input coupled to the pulse generator to receive the pulses. The clock generator circuit includes a phase detector configured to compare the output clock and the reference clock and generate the phase error signal, and a control circuit configured to generate the first and second control codes based on the phase error signal.

    ADJUSTABLE BUFFER CIRCUIT
    6.
    发明公开
    ADJUSTABLE BUFFER CIRCUIT 审中-公开
    可调缓冲器电路

    公开(公告)号：EP3281294A1

    公开(公告)日：2018-02-14

    申请号：EP15816596.9

    申请日：2015-12-01

    Applicant: Xilinx, Inc.

    Inventor： ZHANG, Wenfeng ,  UPADHYAYA, Parag

    IPC: H03K19/0185 ,  H03K19/094

    CPC classification number: H03K19/018514 ,  H03K19/09432

    Abstract: A common mode logic buffer device includes a current source configured to provide a source current. An input stage includes a first MOS transistor pair configured to generate, from the source current and based upon an input differential voltage, a differential current between two output paths. An output stage includes a second MOS transistor pair configured to generate an output differential voltage based upon an effective impedance provided for the each of the two output paths. An adjustment circuit is configured to adjust, in response to a control signal, the effective impedance of the second MOS transistor pair.

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