公开(公告)号：WO1994026523A1

公开(公告)日：1994-11-24

申请号：PCT/US1994005066

申请日：1994-05-03

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  STORTZ, James, L. ,  WALLACE, David, B.

IPC: B41J02/045

CPC classification number: B41J2/04581 ,  B41J2/04541 ,  B41J2/14209 ,  B41J2202/10

Abstract: A switched digital drive system is used to actuate an ink jet printhead (10) having a spaced, parallel series of internal ink receiving channels (32) opening outwardly at front ends thereof through ink discharge orifices (24) formed in the printhead body (14). The channels are laterally bounded by a spaced series of piezoelectrically deflectable internal sidewall sections of the printhead body interdigitated with the channels. The drive system (12) includes a series of electrical actuation leads (28) each connected to a different one of the sidewall sections (34a), and dual transistor switch structures connected in the leads with each switch, in turn, connected to positive and negative DC voltage sources. To actuate a selected channel, the switches associated with its opposite bounding sidewall sections are operated in a manner sequentially (1) deflecting the sidewall sections outwardly away from initially undeflected positions thereof by imposing constant, opposite polarity voltages thereon, (2) reversing the polarities of the constant voltages to deflect the sidewall sections into the channel, and then (3) imposing a series of voltage pulses of sequentially opposite polarities on each of the inwardly deflected sidewall sections to controllably return them to their initial undeflected positions.

Abstract translation: 切换数字驱动系统用于致动喷墨打印头（10），喷墨打印头（10）具有间隔开的平行的一系列内部油墨接收通道（32），其通过形成在打印头主体（14）中的喷墨孔（24）的前端向外打开 ）。 这些通道由与通道相互指向的打印头主体的间隔开的一系列可压电偏转的内部侧壁部分横向界定。 驱动系统（12）包括一系列电致动引线（28），每个连接到不同的一个侧壁部分（34a），并且每个开关连接到引线中的双晶体管开关结构又连接到正极和 负直流电压源。 为了致动所选择的通道，与其相对的边界侧壁部分相关联的开关以顺序地操作（1）通过在其上施加恒定的相反极性电压使侧壁部分偏离其初始未偏转位置，（2）使极性反转 的恒定电压以将侧壁部分偏转到通道中，然后（3）在每个向内偏转的侧壁部分上施加一系列具有相反极性的电压脉冲，以可控制地将它们返回到它们的初始未偏转位置。

公开(公告)号：WO1994026521A1

公开(公告)日：1994-11-24

申请号：PCT/US1994005060

申请日：1994-05-04

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  WILLIAMSON, Ralph, K. ,  STORTZ, James, L.

IPC: B41J02/045

CPC classification number: B41J2/04581 ,  B41J2/04588 ,  B41J2202/10

Abstract: A digital driver (12) for an ink jet printhead (10) and an associated method for selectively applying voltage to a piezoelectric sidewall actuator of the printhead. The digital driver includes positive, negative and neutral voltage sources, a first switching element (56) having a first control input (60), a first voltage supply input (62) connected to the positive voltage source and a first output (64), a second switching element (58) having a second control input (61), a second voltage supply input connected to the negative voltage source and a second output (65), and a third switching element (70) having a third control input (71), a third voltage supply input connected to the neutral voltage source and a third output (75). The first, second and third outputs are connected together to provide a common output (28) for connection to the piezoelectric sidewall actuator. By asserting the first control input for a first time period, the first switching element (56) generates a positive voltage pulse at the common output to displace the sidewall actuator from a rest position to a first position. Next, by simultaneously deasserting the first control input and asserting the second control input, the second switching element (58) generates a negative voltage pulse at the common output to displace the sidewall actuator from the first position, past the rest position, to a second position. Finally, by deasserting the second control input and asserting the third control input, a path to ground potential is provided at the common output, thereby driving the return of the sidewall actuator to the rest position.

Abstract translation: 一种用于喷墨打印头（10）的数字驱动器（12）以及用于向打印头的压电侧壁致动器选择性地施加电压的相关方法。 数字驱动器包括正，负和中性电压源，具有第一控制输入（60）的第一开关元件（56），连接到正电压源的第一电压供应输入端（62）和第一输出端（64）， 具有第二控制输入（61）的第二开关元件（58），连接到所述负电压源的第二电压源输入端和第二输出端（65），以及具有第三控制输入端（71）的第三开关元件 ），连接到中性电压源的第三电压电源输入端和第三输出端（75）。 第一，第二和第三输出端连接在一起以提供用于连接到压电侧壁致动器的公共输出端（28）。 通过在第一时间段内确定第一控制输入，第一开关元件（56）在公共输出端产生正电压脉冲，以将侧壁致动器从静止位置移位到第一位置。 接下来，通过同时解除第一控制输入并断言第二控制输入，第二开关元件（58）在公共输出端产生负电压脉冲，以将侧壁致动器从第一位置移动到静止位置， 位置。 最后，通过解除第二控制输入并断言第三控制输入，在公共输出处提供接地电位的路径，从而驱动侧壁致动器返回到静止位置。

公开(公告)号：WO1994025279A1

公开(公告)日：1994-11-10

申请号：PCT/US1994005103

申请日：1994-04-28

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  HAYES, Donald, J. ,  WALLACE, David, B.

IPC: B41J02/16

CPC classification number: B41J2/04581 ,  B23K26/389 ,  B23K2103/42 ,  B23K2103/50 ,  B41J2/0458 ,  B41J2/04593 ,  B41J2/14209 ,  B41J2/1433 ,  B41J2/2128

Abstract: A spot size modulatable, drop-on-demand type ink jet printhead (32) and associated methods for ejecting volume modulatable droplets of ink therefrom. The ink jet printhead (32) includes a main body portion (34) having first and second ink carrying channels (50a, 50b, 50c, 50d) longitudinally extending therethrough and a cover plate (42) fixedly mounted thereto. Formed in the cover plate (42) is a tapered orifice (48a, 48b) which extends from first and second openings (50, 52) along a back side surface to a third opening (54) along a front side surface thereof. The cover plate (42) is mounted to the main body portion (34) such that the first opening (50) is in communication with the first ink carrying channel (50a, 50c) and the second opening (52) is in communication with the second ink carrying channel (50b, 50d). The ink jet printhead (32) further includes first and second actuators (50a, 50b, 50c, 50d) coupled with the first and second ink carrying channels respectively. Volume modulatable droplets of ink may be ejected from the ink jet printhead (32) by simultaneously applying a voltage pulse having a selected magnitude to the first ink carrying channel and a voltage pulse having a magnitude ranging between zero and the selected magnitude to the second ink carrying channel. Alternately, volume modulatable droplets of ink may be ejected from the ink jet printhead by sequentially applying a voltage pulse having a selected time duration to the first ink carrying channel and a voltage pulse having a time duration ranging between zero and the selected time duration to the second ink carrying channel.

Abstract translation: 点尺寸可调节按需喷墨打印头（32）和用于从其中排出油墨的体积可调节液滴的相关方法。 喷墨打印头（32）包括：主体部分（34），其具有纵向延伸穿过的第一和第二墨水容纳通道（50a，50b，50c，50d）和固定地安装在其上的盖板（42）。 在盖板（42）上形成有从第一和第二开口（50,52）沿其前侧表面沿着背侧表面延伸到第三开口（54）的锥形孔口（48a，48b）。 盖板（42）安装在主体部分（34）上，使得第一开口（50）与第一墨水输送通道（50a，50c）连通，第二开口（52）与 第二墨水输送通道（50b，50d）。 喷墨打印头（32）还包括分别与第一和第二墨水输送通道耦合的第一和第二致动器（50a，50b，50c，50d）。 可以通过将具有选定幅度的电压脉冲同时施加到第一墨水承载通道并且具有范围在零和所选大小之间的幅度的电压脉冲到第二墨水从喷墨打印头（32）喷射墨水的体积可调节液滴 携带通道。 或者，可以通过将具有选定持续时间的电压脉冲顺序地施加到第一墨水携带通道和具有从0到所选择的持续时间之间的持续时间范围的电压脉冲，从墨喷射打印头喷射体积可调节的墨水滴 第二墨水通道。

公开(公告)号：WO1994014121A1

公开(公告)日：1994-06-23

申请号：PCT/US1993011847

申请日：1993-12-06

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  WOOTEN, David, R. ,  MILLER, Craig, A. ,  LEIGH, Kevin, B. ,  COSTLEY, Robert, Brett ,  SIMONICH, Christopher, E.

IPC: G06F13/40

CPC classification number: G06F13/4022

Abstract: A point to point connection architecture for a computer I/O subsystem, resulting in a scalable tree structure. A Master I/O Concentrator (MIOC) is connected to the host bus and handles conversion between a bus oriented structure and the tree structure of the I/O subsystem. Ports away from the host bus are downstream ports and conform to a simple byt wide message protocol. Various IOCs and devices can be attached to one of the downstream ports on the MIOC. The MIOC directs transmissions to the appropriate channel based on a geographical addressing scheme. The IOC connections act as further points of branching. Ultimately IOD or I/O devices are reached, having an upstream port for connection to the IOC and a downstream port and internal logic appropriate for the particular peripheral device. Various registers are present in the IOCs and the IODs to allow determination of the topology and particular devices present. Messages and commands are transfered in the I/O subsystem in defined packets. Various read, write and exchange commands are used, with a read response being utilized to allow split transaction read operations. Certain status and control commands are also present. Interrupts are handled by having the interrupt levels correspond to memory addresses of the programmable interrupt controller, thus allowing simple selection of interrupts to be generated by the devices and no need for separate wiring.

Abstract translation: 用于计算机I / O子系统的点对点连接架构，从而产生可扩展的树结构。 主I / O集中器（MIOC）连接到主机总线，处理面向总线的结构与I / O子系统的树结构之间的转换。 远离主机总线的端口是下游端口，并符合简单的直接宽信息协议。 各种IOC和设备可以连接到MIOC的下游端口之一。 MIOC根据地理寻址方案将传输指向适当的信道。 IOC连接充当分支的进一步点。 最终到达IOD或I / O设备，具有连接到IOC的上行端口和下游端口以及适用于特定外围设备的内部逻辑。 各种寄存器存在于IOC和IOD中，以允许确定拓扑和存在的特定设备。 消息和命令在定义的数据包中在I / O子系统中传输。 使用各种读取，写入和交换命令，其中使用读取响应来允许拆分事务读取操作。 还存在某些状态和控制命令。 中断通过使中断电平对应于可编程中断控制器的存储器地址来处理，从而允许简单地选择要由器件产生的中断，而不需要单独的布线。

公开(公告)号：WO1994011999A3

公开(公告)日：1994-05-26

申请号：PCT/US1993010984

申请日：1993-11-08

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  DYKES, Don, A. ,  CASTELL, Robin, T. ,  CLARK, Andrew, C. ,  NAGEL, Paul, E. ,  TRAN, Huyen, B. ,  JONES, Randall, L. ,  BALDRIDGE, Ronald, L.

IPC: H04Q07/04

公开(公告)号：WO1994009436A1

公开(公告)日：1994-04-28

申请号：PCT/US1993009784

申请日：1993-10-04

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  CALLISON, Ryan, A. ,  CHANDLER, Gregory, T. ,  GRIEFF, Thomas, W.

IPC: G06F13/12

CPC classification number: G06F3/0601 ,  G06F12/0866 ,  G06F13/124 ,  G06F2003/0692

Abstract: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycle to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM. The ADAC obtains the CDB, loads the data into registers and then performs operations according to the information contained in these registers until a transfer is done. The ADAC itself performs operations, including automatic stripe scattering and gathering to develop contiguous host memory fields from striped array data. A series of CDBs can be chained so that a complex series of tasks can be developed. In one variation a string of CDBs is developed to transfer data but some data is transferred to the bit bucket, while other data is actually transferred.

Abstract translation: 一种磁盘阵列控制器板，其使用作为其内部数据总线上的从机的EISA总线主机，以允许先进的驱动器阵列控制器芯片（ADAC）作为主机操作。 ADAC连接到传输缓冲RAM。 内部数据总线的协议提供了将主机存储器地址加载到总线从站中的周期，以提供传输计数信息和从属特定信息以及一系列数据传输周期。 本地处理器连接到EISA总线主控和ADAC控制操作并提供某些信息。 ADAC由称为命令描述符块（CDB）的结构控制。 每个CDB包括描述ADAC用于执行其传送操作的各种地址，控制位和功能位的信息。 本地处理器直接将形成CDB的数据写入并存储到传送缓冲器RAM中。 ADAC获得CDB，将数据加载到寄存器中，然后根据这些寄存器中包含的信息执行操作，直到传输完成。 ADAC本身执行操作，包括自动条纹散射和收集，以从条形阵列数据开发连续的主机内存字段。 一系列CDB可以链接，以便可以开发一系列复杂的任务。 在一个变化中，开发了一串CDB来传输数据，但是一些数据被传送到比特桶，而其他数据被实际传输。

公开(公告)号：WO1994008306A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009364

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  GALLOWAY, William, C.

IPC: G06F13/42

CPC classification number: G06F13/4226

Abstract: An SCSI device resides and communicates on the SCSI bus without that device being assigned an SCSI address or corresponding SCSI ID. The driver software on the host computer directs the SCSI initiator device to select itself as its target, so the initiator then only asserts one bit of the eight bit SCSI data bus. The SCSI device determines when a SELECTION phase is under way and then determines if only one bit has been asserted on the SCSI data bus. The SCSI device then responds to the initiator as being the target device, thus completing the SELECTION phase. The initiator and the SCSI device can then communicate as a normal initiator and target would during information transfer stages of the SCSI standard. This is all done without the SCSI device occupying a normal SCSI address.

Abstract translation: SCSI设备驻留并在SCSI总线上进行通信，而不会为该设备分配SCSI地址或相应的SCSI ID。 主机上的驱动程序软件指示SCSI启动器设备将其自身选为其目标，因此启动器只会断言8位SCSI数据总线的一位。 SCSI设备确定SELECTION阶段何时正在进行，然后确定SCSI数据总线上是否只有一个位被置位。 然后，SCSI设备作为目标设备响应发起者，从而完成SELECTION阶段。 然后，启动器和SCSI设备可以在SCSI标准的信息传输阶段中作为正常启动器和目标进行通信。 没有SCSI设备占用正常的SCSI地址就完成了。

公开(公告)号：WO1994008303A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009430

申请日：1993-09-30

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  FRY, Walter, G. ,  WOLFORD, Jeff, W.

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F12/0831

Abstract: A method and apparatus which reduces the non-snoop window of a cache controller during certain operations to increase host bus efficiency. The cache controller requires a bus grant signal to perform cycles and cannot snoop cycles after the bus grant signal has been provided until the cycle completes. Cache interface logic monitors the cache controller for cycles that require either the expansion bus or the local I/O bus. When such a cycle is detected, the apparatus begins the cycle and does not assert the bus grant signal to the cache controller. The cache controller thus believes that the cycle has not yet begun and is thus able to perform other operations, such as snooping other host bus cycles. During this time, the cycle executes. When the read data is returned or when the write data reaches its destination, the interface logic provides the bus grant cycle to the cache controller at an appropriate time. By delaying the bus grant signal in this manner, the non-snoop window is reduced.

Abstract translation: 一种在某些操作期间减少高速缓存控制器的非窥探窗口以增加主机总线效率的方法和装置。 高速缓存控制器需要总线授权信号来执行周期，并且在提供总线授权信号直到循环完成之后才能窥探周期。 缓存接口逻辑监控缓存控制器的周期，这些周期需要扩展总线或本地I / O总线。 当检测到这样的周期时，设备开始周期，并且不向总线授权信号断言到高速缓存控制器。 因此，高速缓存控制器认为该周期尚未开始，因此能够执行其他操作，例如窥探其他主机总线周期。 在此期间，循环执行。 当读取数据返回或写数据到达其目的地时，接口逻辑在适当的时间向缓存控制器提供总线授权周期。 通过以这种方式延迟总线授权信号，减少非窥视窗口。

公开(公告)号：WO1994006570A1

公开(公告)日：1994-03-31

申请号：PCT/US1993008396

申请日：1993-09-03

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  HAYES, Donald, J.

IPC: B05D01/00

CPC classification number: B05C11/08 ,  B05D1/005 ,  Y10T428/24777 ,  Y10T428/24793 ,  Y10T428/24802 ,  Y10T428/265 ,  Y10T428/31504

Abstract: A method for film coated passivation of individual grooves or channels in an array of closely spaced grooves or channels of a workpiece, for example, ink channels in a printhead employed in an ink jet printer device; includes the steps of placing the workpiece on a rotation plate having a rotational center, securing the workpiece to the rotation plate with the grooves directed radially outward from the rotational center of the rotation plate, placing resin upon the workpiece in the vicinity of the grooves, and spinning the rotation plate to cause the resin to migrate along the surfaces of the grooves and thereby coating them.

Abstract translation: 用于在喷墨打印机装置中使用的打印头中的油墨通道的工件的紧密间隔的凹槽或通道的阵列中的单个凹槽或通道的薄膜涂覆钝化的方法; 包括将工件放置在具有旋转中心的旋转板上的步骤，将工件固定到旋转板上，其中凹槽从旋转板的旋转中心径向向外指向，将树脂放置在工件附近的凹槽中， 并旋转旋转板以使树脂沿着凹槽的表面迁移并由此涂覆。

公开(公告)号：WO1993022726A1

公开(公告)日：1993-11-11

申请号：PCT/US1993004006

申请日：1993-04-28

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  WUNDERLICH, Russell, J. ,  TAYLOR, Mark ,  STANCIL, Charles, J. ,  HUNSAKER, Mikal, C. ,  BELMONT, Brian, V.

IPC: G06F12/06

CPC classification number: G06F12/0653 ,  G06F12/1433

Abstract: A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided. The RAM is only programmed once, with modifications to the RAM-provided write protect status and memory location values being made based on write protect and relocation status information contained in a separate register.

Abstract translation: 存储器映射和模块使能电路，用于允许为连接到存储器系统的任何模块中的任何位置定义逻辑128K字节的存储器块。 RAM由定义128千字节块的系统地址线寻址，输出数据为特定存储器模块提供行地址选通使能信号，以及将128K字节块放置在模块内所需的地址值。 各种其他参数，如写保护状态和存储器位置也由RAM提供。 提供了用于编程和读取RAM的电路和技术。 RAM仅被编程一次，修改RAM提供的写保护状态和存储位置值是基于单独寄存器中包含的写保护和重定位状态信息进行的。