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    SEMICONDUCTOR INTEGRATED CIRCUIT AND NONVOLATILE MEMORY ELEMENT
    81.
    发明授权
    SEMICONDUCTOR INTEGRATED CIRCUIT AND NONVOLATILE MEMORY ELEMENT 有权
    集成电路和半导体非易失性存储元件

    公开(公告)号：EP1150302B1

    公开(公告)日：2010-01-06

    申请号：EP00900823.6

    申请日：2000-01-19

    Applicant: Renesas Technology Corp.

    Inventor： SYUKURI, Syoji ,  KOMORI, Kazuhiro ,  OKUYAMA, Kousuke ,  KUBOTA, Katsuhiko

    IPC: G11C16/06 ,  G11C16/04

    CPC classification number: H01L27/11526 ,  B82Y10/00 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/28 ,  G11C16/349 ,  G11C2216/08 ,  G11C2216/10 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11546 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

    Abstract: A nonvolatile memory element (130) constituting a flash memory is constructed such that a gate oxide film (GO2) and a gate electrode (GT2) of a transitor of another circuit formed over the same semiconductor substrate are a tunnel oxide film (GO3) and a floating gate electrode (FGT), respectively. One memory cell has a two-element one-bit construction composed of a pair of nonvolatile memory elements connected with paired complementary data lines. For the paired nonvolatile memory elements, threshold voltage states which are different from each other are set up so that they are differentially read. A word line voltage in reading operation is substantially equal to a threshold voltage (initial threshold voltage) in a thermal by equilibrium state of the non-volatile memory elements, desirably to an average of the low threshold voltage and the high threshold voltage of the memory elements. No matter whether the paired nonvolatile memory elements may be in the high threshold voltage state or in the low threshold voltage state, their threshold voltage are liable to approach the initial threshold voltage asymptotically to deteriorate in their characteristics. At this time, a word line selecting voltage is substantially equal to the initial threshold voltage, so that the read failure hardly occurs even if the characteristic deterioration of one memory element progresses relatively.

    Semiconductor device with shared contact hole for gate electrode and drain region
    83.
    发明公开
    Semiconductor device with shared contact hole for gate electrode and drain region 审中-公开
    Halbleitervorrichtung mit geteiltem KontaktlochfürGate-Elektrode und Drain-Gebiet

    公开(公告)号：EP2075831A2

    公开(公告)日：2009-07-01

    申请号：EP08254137.6

    申请日：2008-12-23

    Applicant: Renesas Technology Corp.

    Inventor： Takeuchi, Masahiko , Renesas Technology Corp.

    IPC: H01L21/8239 ,  H01L21/8244 ,  H01L27/02 ,  H01L27/105 ,  H01L27/11 ,  H01L21/027 ,  H01L21/768

    CPC classification number: H01L27/1104 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L29/4238

    Abstract: Shared contact holes SC1 and SC2 reach both gate electrode layers GE1 and GE2 and a drain region PIR. In a planar view, a sidewall E2 of gate electrode layers GE1 and GE2 is shifted toward a side of a sidewall E4 from a virtual extended line E1a of the sidewall E1. In a planar view, a center line (C2-C2) of a line width D1 in a portion that shared contact holes SC1 and SC2 of gate electrode layers GE1 and GE2 reach is located while shifted with respect to a center line (C1-C1) of a line width D2 in a portion located on channel formation regions CHN1 and CHN2 of gate electrode layers GE1 and GE2. Therefore, a semiconductor device such as an SRAM or TCAM and a photomask that can suppress an opening defect of the shared contact hole are obtained.

    Abstract translation: 共用接触孔SC1和SC2到达栅极电极层GE1和GE2以及漏极区PIR。 在平面图中，栅电极层GE1和GE2的侧壁E2从侧壁E1的虚拟延伸线E1a向侧壁E4侧移动。 在平面图中，在共享栅极电极层GE1和GE2的接触孔SC1和SC2的共享部分中的线宽度D1的中心线（C2-C2）位于相对于中心线（C1-C1 ）位于栅极电极层GE1和GE2的沟道形成区域CHN1和CHN2的部分中的线宽度D2。 因此，可以获得诸如SRAM或TCAM的半导体器件和可以抑制共享接触孔的开口缺陷的光掩模。

    SEMICONDUCTOR DEVICE
    86.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：EP2023274A1

    公开(公告)日：2009-02-11

    申请号：EP07743452.0

    申请日：2007-05-16

    Applicant: Renesas Technology Corp.

    Inventor： NISHIZAWA, Hirotaka, c/o RENESAS TECHMOLOGY CORP. ,  OSAKO, Junichiro, c/o RENESAS TECHNOLOGY CORP. ,  SHINOHARA, Minoru, c/o RENESAS EASTERN JAPAN SEMICONDUCTOR INC. ,  WADA, Tamaki, c/o RENESAS TECHNOLOGY CORP. ,  KATAYAMA, Kunihiro, c/o RENESAS TECHNOLOGY CORP. ,  SHIOTA, Shigemasa, c(o RENESAS TECHNOLOGY CORP.

    IPC: G06K19/07

    CPC classification number: G06K19/077 ,  G06K19/0719 ,  G06K19/072

    Abstract: A semiconductor device has operation modes selectable through the control by a second microcomputer (113). In a first mode, an operation of a memory controller (105) responding to a memory card command from a memory card interface terminal and an operation of a first microcomputer (106) responding to an IC card command from an IC card interface terminal are separately performed. In a second mode, the first microcomputer operates in response to the IC card command from the IC card interface terminal. In a third mode, the memory controller and the first microcomputer operate in response to an undefined IC card command from the IC card interface terminal. In a fourth mode, the memory controller and the first microcomputer operate in response to the memory card command from the memory card interface terminal. Convenience of the semiconductor device having an IC card function and a memory card function is improved.

    Abstract translation: 半导体器件具有通过第二微型计算机（113）的控制可选择的操作模式。 在第一模式中，存储器控制器（105）响应来自存储卡接口端子的存储卡命令的操作和响应来自IC卡接口端子的IC卡命令的第一微型计算机（106）的操作分别是 执行。 在第二模式中，第一微型计算机响应来自IC卡接口终端的IC卡命令而操作。 在第三模式中，存储器控制器和第一微型计算机响应于来自IC卡接口终端的未定义的IC卡命令而操作。 在第四模式中，存储器控制器和第一微型计算机响应于来自存储卡接口终端的存储卡命令而操作。 改善具有IC卡功能和存储卡功能的半导体器件的便利性。

    Method of forming resist pattern and semiconductor device manufactured with the same
    90.
    发明公开
    Method of forming resist pattern and semiconductor device manufactured with the same 审中-公开
    Verfahren zur Resiststrukturbildung und damit hergestellte Halbleitervorrichtung

    公开(公告)号：EP1975719A3

    公开(公告)日：2008-12-24

    申请号：EP08005983.5

    申请日：2008-03-28

    Applicant: Renesas Technology Corp.

    Inventor： Ishibashi, Takeo ,  Terai, Mamoru ,  Hagiwara, Takuya ,  Yamaguchi, Atsumi

    IPC: G03F7/11 ,  G03F7/20 ,  G03F7/09 ,  G03F7/16

    CPC classification number: G03F7/2041 ,  G03F7/11 ,  Y10T428/24835

    Abstract: A method of forming a resist pattern through liquid immersion exposure in which exposure is performed such that a liquid film is formed between a substrate for a semiconductor device on which a processed film is formed and an objective lens arranged above the substrate is provided, and the substrate treated with a water-repellent agent solution composed of at least a water-repellent agent and a solvent is exposed to light.

    Abstract translation: 提供了一种通过液浸曝光形成抗蚀剂图案的方法，其中进行曝光，使得在其上形成有处理膜的半导体器件的基板和布置在基板上方的物镜之间形成液膜，并且 用至少由拒水剂和溶剂组成的拒水剂溶液处理的基材曝光。

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