公开(公告)号：US20150261342A1

公开(公告)日：2015-09-17

申请号：US14213250

申请日：2014-03-14

Applicant: SILICON INTEGRATED SYSTEMS CORP

Inventor： JIH-MING HSU ,  CHIA-YI CHU ,  CHIN-HUA KUO

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F3/0416

Abstract: A capacitive touch device and a sensing method thereof are disclosed. The capacitive touch device includes a touch panel, at least one touch detection unit and a processing unit. The touch detection unit scans the touch panel, obtains an N-bit sensed data and compresses the N-bit sensed data to an L-bit sensed data. The processing unit receives the L-bit sensed data, decompresses the L-bit sensed data to the N-bit sensed data and calculates a coordinate of a touch according to the N-bit sensed data. The present invention is capable of decreasing the time for transmitting the sensed data, the power consumption and the requirements for the memory capacity of the touch detection unit and the memory capacity of the processing unit.

Abstract translation: 公开了电容式触摸装置及其感测方法。 电容式触摸装置包括触摸面板，至少一个触摸检测单元和处理单元。 触摸检测单元扫描触摸面板，获得N位感测数据，并将N位感测数据压缩为L位感测数据。 处理单元接收L位检测数据，将L位检测数据解压缩为N位检测数据，并根据N位检测数据计算触摸坐标。 本发明能够减少发送感测数据的时间，功耗以及触摸检测单元的存储容量的要求和处理单元的存储容量。

公开(公告)号：US20040208389A1

公开(公告)日：2004-10-21

申请号：US10413282

申请日：2003-04-15

Applicant: SILICON INTEGRATED SYSTEMS CORP.

Inventor： Wen-Kuo Lin

IPC: G06K009/40

CPC classification number: G06T5/002 ,  G06T5/10 ,  G06T5/20 ,  G06T2207/20012 ,  G06T2207/20021 ,  G06T2207/20052 ,  G06T2207/20192 ,  H04N19/423 ,  H04N19/86

Abstract: A digital picture processing method for mainly partitioning an inputted picture into a plurality of blocks and then separately performing a deblocking process and a deringing process on each of the blocks so as to reduce the required memory space and to instantaneously process the data.

Abstract translation: 一种数字图像处理方法，主要将输入的图像分割成多个块，然后分别对每个块分别执行去块处理和去打印处理，以便减少所需的存储空间并且即时处理数据。

公开(公告)号：US20040208384A1

公开(公告)日：2004-10-21

申请号：US10418198

申请日：2003-04-18

Applicant: SILICON INTEGRATED SYSTEMS CORP.

Inventor： Wen-Kuo Lin ,  Chung-Yen Lu

IPC: G06K009/40 ,  G06K009/32

CPC classification number: H04N7/012 ,  H04N7/0137 ,  H04N7/0142

Abstract: A method for motion pixel detection with adaptive thresholds, according to the global motion information among the reference video fields, so as to correctly evaluate whether a missing pixel is in a static region or a non-static region, thereby reconstructing the missing pixel by an inter-field interpolation process or an intra-field interpolation process. If the amount of motion among the reference fields is large, there is high motion information among the reference fields, so the threshold is set to be small; if the amount is small, there is less motion information between the reference fields, and so the threshold should be set to be large.

Abstract translation: 一种根据参考视频场中的全局运动信息的具有自适应阈值的运动像素检测的方法，以便正确地评估缺失像素是在静态区域还是非静态区域中，从而通过以下方式重建缺失像素： 场间插值处理或场内插值处理。 如果参考场之间的运动量大，则在参考场中存在高运动信息，所以阈值被设定得很小; 如果量少，则参考场之间的运动信息较少，因此阈值应该设置得很大。

公开(公告)号：US20040181722A1

公开(公告)日：2004-09-16

申请号：US10401701

申请日：2003-03-31

Applicant: Silicon Integrated Systems Corp.

Inventor： Juinn Lee ,  Chin-Pin Jen ,  Ming-Chang Yang ,  Hung-Chieh Chen

IPC: G01R031/28 ,  H03M013/00

CPC classification number: G01R31/318569 ,  G01R31/318566 ,  G01R31/3191

Abstract: For a plurality of logic integrated circuits, initial value vectors associated with flip-flops are retrieved from each of corresponding scan chain sets. The initial value vectors of the same corresponding scan chain set are compared with each other so as to identify elements with fixed values in the initial value vectors. When the total number of the elements with fixed values reaches a predetermined percentage, the elements having fixed values are selected as a golden pattern of the corresponding scan chain set. During the testing, an initial value vector of a scan chain of a logic integrated circuit to be tested is compared with the golden pattern associated with the scan chain, so as to determine whether a faulty flip-flop exists in the scan chain of the logic integrated circuit to be tested.

Abstract translation: 对于多个逻辑集成电路，从每个对应的扫描链集中检索与触发器相关联的初始值向量。 将相同对应的扫描链集合的初始值向量彼此进行比较，以便在初始值向量中识别具有固定值的元素。 当具有固定值的元素的总数达到预定百分比时，具有固定值的元素被选择为相应的扫描链集合的金色图案。 在测试期间，将要测试的逻辑集成电路的扫描链的初始值向量与与扫描链相关联的黄金模式进行比较，以确定在逻辑的扫描链中是否存在故障触发器 集成电路进行测试。

公开(公告)号：US20030063621A1

公开(公告)日：2003-04-03

申请号：US09964478

申请日：2001-09-28

Applicant: SILICON INTEGRATED SYSTEMS CORP.

Inventor： Ching-Kae Tzou ,  Shih-Chung Yin ,  Shuenn-Ren Liu ,  Min-Chieh Chen

IPC: H04L012/413

CPC classification number: H04L12/413 ,  H04L2012/40247

Abstract: A collision detection method for a multiple access communication system is disclosed. By using the error term of a time-domain equalized signal as a detection source, an operation on the error term can be performed to determine whether collision occurs. For example, the mean square error and/or maximum value of the real part and/or imaginary part of the error term can be calculated or selected to distinguish the collision and non-collision situations. A collision detection apparatus for a multiple access communication system is also disclosed. The collision detection apparatus utilizes an existent adaptive equalizer and signal processing device for obtaining received information data bits to obtain the error term. The error term is further processed by a mean-square-error or maximum-absolute-value operator to determine the collision status.

Abstract translation: 公开了一种用于多址通信系统的冲突检测方法。 通过使用时域均衡信号的误差项作为检测源，可以执行错误项的操作以确定是否发生冲突。 例如，可以计算或选择误差项的实部和/或虚部的均方误差和/或最大值以区分碰撞和非碰撞情况。 还公开了一种用于多址通信系统的冲突检测装置。 冲突检测装置利用现有的自适应均衡器和信号处理装置来获得接收的信息数据比特以获得误差项。 误差项由均方误差或最大绝对值算子进一步处理，以确定碰撞状态。

公开(公告)号：US20020167090A1

公开(公告)日：2002-11-14

申请号：US10108611

申请日：2002-03-27

Applicant: Silicon Integrated Systems Corp.

Inventor： Chen-Chiu Hsue ,  Shyh-Dar Lee

IPC: H01L029/40 ,  H01L023/52 ,  H01L023/48

CPC classification number: H01L21/76807 ,  H01L23/5223 ,  H01L28/55 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention provides a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

Abstract translation: 本发明提供一种具有电容器的双镶嵌结构。 在形成薄膜电容器之前，通过镶嵌工艺用Cu金属制造底层互连。 电容器通过沉积第一金属层，绝缘体和第二金属层而形成。 然后，对堆叠的层进行两次掩模和蚀刻处理以形成薄膜电容器和金属线。 在形成电容器之后，通过镶嵌工艺用Cu金属制造上互连。

公开(公告)号：US20020155695A1

公开(公告)日：2002-10-24

申请号：US09841568

申请日：2001-04-19

Applicant: Silicon Integrated Systems Corp.

Inventor： Shyh-Dar Lee ,  Chen-Chiu Hsue

IPC: H01L021/4763 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L21/0223 ,  H01L21/0212 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A dual damascene process is applied on a semiconductor substrate having a dual damascene opening with a via hole which exposes a metal wire and is surrounded by a first low-k dielectric layer, and a trench which is over the via hole and surrounded by a second low-k dielectric layer. An in-situ oxide liner, serving as a dielectric barrier layer, is formed on the sidewall of the first low-k dielectric layer and the second low-k dielectric layer. A metal barrier layer is conformally deposited on the exposed surface of the semiconductor substrate to cover the sidewall and bottom of the dual damascene opening. The dual damascene opening is filled with a conductive layer, and then the excess conductive layer outside the trench level is polished away by a CMP process.

Abstract translation: 双镶嵌工艺应用于具有双镶嵌开口的半导体衬底，其具有暴露金属线并被第一低k电介质层包围的通孔，以及位于通孔上方并被第二个 低k电介质层。 用作介电阻挡层的原位氧化物衬垫形成在第一低k电介质层和第二低k电介质层的侧壁上。 金属阻挡层共形沉积在半导体衬底的暴露表面上以覆盖双镶嵌开口的侧壁和底部。 双镶嵌开口填充有导电层，然后通过CMP工艺抛光沟槽水平面外的剩余导电层。

公开(公告)号：US20240388113A1

公开(公告)日：2024-11-21

申请号：US18664966

申请日：2024-05-15

Applicant: SILICON INTEGRATED SYSTEMS CORP.

Inventor： Song Sheng LIN ,  Keng-Nan CHEN

IPC: H02J7/00

Abstract: A constant current charging device is configured to charge a device to be charged and includes: a reference current source configured to provide a reference current; a current mirror electrically coupled to the reference current source and configured to output a mirror current; a current adjustment control unit electrically coupled to the current mirror and the device to be charged wherein the current adjustment control unit is configured to output a charging current according to the mirror current to charge the device to be charged; and a current compensation unit electrically coupled to the current mirror and the current adjustment control unit. The current adjustment control unit includes a voltage follower unit, and the current adjustment control unit tracks a charging voltage through the voltage follower unit to stabilize the charging current.

公开(公告)号：US20230078321A1

公开(公告)日：2023-03-16

申请号：US17930249

申请日：2022-09-07

Applicant: Silicon Integrated Systems Corp.

Inventor： Min-han Lee

IPC: G06F3/0354 ,  G06F3/038 ,  H04M1/72412 ,  G06F3/041

Abstract: An interactive control system includes: an active pen; and an electronic device configured to wirelessly control the active pen, receive a user command, and generate a control command according to the user command, wherein at least one of the active pen and the electronic device is configured to execute a control function according to the control command.

公开(公告)号：US20210305835A1

公开(公告)日：2021-09-30

申请号：US17205002

申请日：2021-03-18

Applicant: Silicon Integrated Systems Corp.

Inventor： Song-Sheng LIN ,  Keng-Nan CHEN

IPC: H02J7/00 ,  G05F3/26

Abstract: A constant current charging device is configured to charge a device to be charged and includes: a reference current source configured to provide a reference current; a current mirror electrically coupled to the reference current source and configured to output a mirror current; a current adjusting unit electrically coupled to the current mirror and the device to be charged and configured to output a charging current according to the mirror current to charge the device to be charged; and a current compensation unit electrically coupled to the current mirror and the current adjusting unit and configured to adjust the charging current according to a reference voltage.