中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

911 records (took 0.024 seconds)

    SCSI CONVERTER
    81.
    发明专利
    SCSI CONVERTER 失效

    公开(公告)号：JPH02110649A

    公开(公告)日：1990-04-23

    申请号：JP15938689

    申请日：1989-06-21

    Applicant: TANDEM COMPUTERS INC

    Inventor： JIEIMUZU EDOWAADO KOOPII

    IPC: G06F13/36 ,  G06F13/40 ,  G06F13/42 ,  H04L12/413

    Abstract: PURPOSE: To completely use all the capability of the SCSI protocol by transmitting a BSY signal from inside to outside only when PIB signals are set and from outside to inside only when PEB signals are set. CONSTITUTION: The BUSY(BSY) signal is sent from inside to outside only when PASS, INT, and BSY(PIB) signals are set by an inside-to-outside receiver and driver pair 34 and an outside-to-inside receiver and driver pair 36 and from outside to inside only when PASS, EXT, and BSY(PEB) signals are set. The PIB signals are sent when a bus in bus free or arbitration phase and an outside device asserts its device ID. Therefore, a device on one side of the converter 10 sends its BSY signal to the other side during the arbitration phase.

    PARITY REPRODUCTION SELF-CHECKING
    82.
    发明专利
    PARITY REPRODUCTION SELF-CHECKING 失效

    公开(公告)号：JPH01280838A

    公开(公告)日：1989-11-13

    申请号：JP30046288

    申请日：1988-11-28

    Applicant: TANDEM COMPUTERS INC

    Inventor： MAATEIN DABURIYUU SANAA

    IPC: G06F11/10

    Abstract: PURPOSE: To ensure the detection and separation of errors by monitoring the completeness of data made to cross the input boundary of a digital sub system and transmitted through various combination logic provided inside the boundary to the output of the sub system. CONSTITUTION: Three points for checking the completeness of the data, that are a parity checking circuit 30, the parity checking circuit 48 and exclusive OR and AND gates 50 and 52, are provided inside the sub system 10. Then, the check points are provided with three error signals, that are a bus A error, a parity reproduction error and a bus B error, and they successively give the instruction of a part where the error is generated. Thus, the generation of a parity error on the sub system is surely checked and separated.

    STACK WITH SINGLE ENCODED STACK POINT
    83.
    发明专利
    STACK WITH SINGLE ENCODED STACK POINT 失效

    公开(公告)号：JPH01269293A

    公开(公告)日：1989-10-26

    申请号：JP8626488

    申请日：1988-04-07

    Applicant: TANDEM COMPUTERS INC

    Inventor： DANIERU II RENOOSUKI

    IPC: G11C7/00 ,  G06F7/78 ,  G06F9/34

    Abstract: PURPOSE: To eliminate the need for decoding logic and to simplify a structure by shifting a pointer toward the right or left as a data element is pushed onto a stack or is popped therefrom. CONSTITUTION: The input of a register 26 where the bit of digital 1 receives the first data element of the stack under a load constant is enabled in an example of a last-in first-out LIFO. The pointer is circulated to the left in such a manner that the input of the register 32 is enabled at the time of adding the next data element. In the case of the pop operation to fetch the uppermost data element of the stack, an enable signal is applied to a line 46 to enable the output driver 38 for the register 30 and the pointer is circulated to the right so as to indicate the register 32. The pointer in the stack 24 is circulated and the input data element is not applied to the input bus 34 until the pointer indicates the empty register in the writing operation. The output 36 is read before the circulation of the pointer in the stack 24 in such a manner that the uppermost data element is read in the reading operation.

    CONTROLLER FOR CONNECTING ELECTRIC MODULE WITH ELECTRIC SOCKET
    84.
    发明专利
    CONTROLLER FOR CONNECTING ELECTRIC MODULE WITH ELECTRIC SOCKET 失效

    公开(公告)号：JPS6489395A

    公开(公告)日：1989-04-03

    申请号：JP14921788

    申请日：1988-06-16

    Applicant: TANDEM COMPUTERS INC

    Inventor： RANDARU JIEI DEIAASU

    IPC: G06F1/16 ,  G06F1/18 ,  H01R13/707 ,  H05K7/14

    Abstract: PURPOSE: To perform required control of an electric connector through a small and simple constitution by an arrangement wherein decoupling of the electric connector is blocked through a stopping member at a position where a switch actuator supplies a current. CONSTITUTION: When the switch 18 of a module 8 coupled with a socket 12 through electric connectors 14, 15 is operated, a switch actuator is shifted from nonconducting position to conducting position for the module 8. At the same time, a handle member 28 interlocked with the switch actuator is lowered and the module 8 is stopped by a stopper 30 integrated with the member 28 thus preventing the connectors 14, 15 from being decoupled. Consequently, generation of spark due to electrical decoupling is prevented during conduction and coupling of the electric connector is satisfactorily controlled through a small and simple constitution.

    METHOD AND APPARATUS FOR DATA TRANSFER HAND SHAKE PIPELINE
    85.
    发明专利
    METHOD AND APPARATUS FOR DATA TRANSFER HAND SHAKE PIPELINE 失效

    公开(公告)号：JPS6457354A

    公开(公告)日：1989-03-03

    申请号：JP9804688

    申请日：1988-04-20

    Applicant: TANDEM COMPUTERS INC

    Inventor： JIYOODAN AARU SHIRUBUAA

    IPC: G06F13/12 ,  G06F13/42

    Abstract: PURPOSE: To shorten the waiting time of a CPU by controlling a data transfer handshape protocol so that the final result of a pending protocol event can be defined later. CONSTITUTION: The CPU 4 transfers data between the CPU 4 itself and an I/O channel 8 every five processor clock cycles. At the initial time of a set of five clock cycles, the CPU 4 sets data on a data bus 12 (at the time of data. reception, it is supposed that the data are put on the data bus 12) and generates a transfer request (SPU-XFR) signal. At the time of receiving a data acception(DTA-ACC) signal, the end of preceding data transfer is supposed. When a transfer completion signal is not generated, a transer inhibit signal for inhibiting the generation of a succeeding DATA-ACC signal is generated, so that the CPU 4 inspects a cause of failing the completion and cancels or reexecutes the preceding data transfer.

    INLET POINT MAPPING AND SKIPPING METHOD AND APPARATUS
    86.
    发明专利
    INLET POINT MAPPING AND SKIPPING METHOD AND APPARATUS 失效

    公开(公告)号：JPS644833A

    公开(公告)日：1989-01-10

    申请号：JP8889588

    申请日：1988-04-11

    Applicant: TANDEM COMPUTERS INC

    Inventor： PIITAA ERU FUU ,  DANIERU II RENOOSUKI

    IPC: G06F9/22 ,  G06F9/26

    Abstract: PURPOSE: To make a microcode changeable by varying the number of address locations for every instruction while maintaining a fixed entrance point mapping system. CONSTITUTION: A variable incrementer 66 is provided with a +1 incrementer 70, +512 incrementer 72 and multiplexer(MUX) 74. At the time of operating, an address to be applied to a microcode memory RAM 32 is incremented just for 512 by the incrementer 72, and a new address is guided through the multiplexer 74 to a microcode program counter(PC) register 36. Until a memory area decode circuit 68 detects that the address corresponds to an overflow area 64, this process is continued. When that is detected, the decode circuit 68 applies a select signal to the multiplexer 74, and the output of the +1 incrementer 70 is selected. Therefore, the address to the microcode memory RAM 32 is incremented one by one.

Patent Agency Ranking