플래시 메모리 장치 및 그것의 워드라인 전압 발생 방법
    81.
    发明公开
    플래시 메모리 장치 및 그것의 워드라인 전압 발생 방법 有权
    闪存存储器件及其线性电压产生方法

    公开(公告)号:KR1020120033724A

    公开(公告)日:2012-04-09

    申请号:KR1020100095406

    申请日:2010-09-30

    Abstract: PURPOSE: A flash memory device and a method for generating a word line voltage thereof are provided to efficiently read and verify data distributed in a negative voltage domain by converting a negative word line voltage level at high speed. CONSTITUTION: It is discriminated whether a negative voltage is continuously generated(S1000). It is determined whether a negative charge pumping result is equal to or lower than a target negative voltage(S1100). If the negative voltage is not continuously generated, a negative charge is pumped. If the target negative voltage is higher than a prior target negative voltage, the output of a negative voltage generator is discharged(S1200). The target negative voltage is generated by pumping the negative charge if the discharge result is higher than the target negative voltage(S1300).

    Abstract translation: 目的:提供闪速存储装置及其字线电压的产生方法,以通过高速转换负字线电压电平来有效地读取和验证分布在负电压域中的数据。 构成:判断是否连续产生负电压(S1000)。 确定负电荷泵送结果是否等于或低于目标负电压(S1100)。 如果不连续产生负电压,则泵送负电荷。 如果目标负电压高于先前的目标负电压,则负电压发生器的输出被放电(S1200)。 如果放电结果高于目标负电压,则通过泵送负电荷来产生目标负电压(S1300)。

    다파장 영상 복원 처리 방법 및 장치와 이를 채용한 의료 영상 시스템
    82.
    发明公开
    다파장 영상 복원 처리 방법 및 장치와 이를 채용한 의료 영상 시스템 无效
    重建图像和医学图像系统的方法和装置启动方法

    公开(公告)号:KR1020120025233A

    公开(公告)日:2012-03-15

    申请号:KR1020100087502

    申请日:2010-09-07

    CPC classification number: G06T11/003 G06T11/005 G06T2211/408

    Abstract: PURPOSE: A multi-wavelength image restoration processing method and apparatus, and a medical image system adopting the same are provided to restore a tomography image of an object to a final image by using a two dimension projected image of the object. CONSTITUTION: An initial value of a tomography image of an object is calculated(101). A weighted value and an error value are calculated based on a measured value(102). An image signal which is measured is transformed(103). An auxiliary variable which is initialized by using a conversion factor which is necessary for changing the image signal is updated(104). The measured value is updated by using the updated auxiliary variable, the calculated weighted value, and the error value(105).

    Abstract translation: 目的:提供多波长图像恢复处理方法和装置以及采用该多波长图像恢复处理方法和装置的医学图像系统,通过使用对象的二维投影图像将对象的断层图像恢复到最终图像。 构成:计算物体的断层图像的初始值(101)。 基于测量值(102)计算加权值和误差值。 测量的图像信号被变换(103)。 通过使用变更图像信号所必需的转换因子进行初始化的辅助变量被更新(104)。 通过使用更新的辅助变量,计算的加权值和误差值(105)来更新测量值。

    유방 촬영 장치 및 그 방법
    83.
    发明公开
    유방 촬영 장치 및 그 방법 有权
    检查乳腺癌的装置和方法

    公开(公告)号:KR1020120010585A

    公开(公告)日:2012-02-06

    申请号:KR1020100069569

    申请日:2010-07-19

    Abstract: PURPOSE: An apparatus and method for photographing a breast are provided to accurately photograph minute lime and breast masses in a breast with low-level irradiation by irradiating X-rays having different energy spectrums on different areas of the breast. CONSTITUTION: An X-ray irradiation part(120) irradiates X-rays of a first energy spectrum and a second energy spectrum to a breast test material. The X-ray irradiation part irradiates the X-rays of a third energy spectrum to a second area which is different from the first area. An X-ray detection part(130) generates a plurality of video frames about a breast by detecting irradiated X-rays which pass through the breast. A video generating part(140) generates video data about the breast by editing the plurality of the video frames. The X-ray irradiation part irradiates the X-rays of a fourth energy spectrum and a fifth energy spectrum to a third area of the breast which is different from a first area.

    Abstract translation: 目的:提供一种用于拍摄乳房的装置和方法,通过在乳房的不同区域上照射具有不同能谱的X射线,以低水平的照射精确地拍摄乳房中的微小石灰和乳房块。 构成:X射线照射部(120)将第一能谱和第二能量谱的X射线照射到乳房检查材料。 X射线照射部将第三能谱的X射线照射到与第一区域不同的第二区域。 X射线检测部(130)通过检测通过乳房的照射X射线来生成关于乳房的多个视频帧。 视频产生部件(140)通过编辑多个视频帧来生成关于乳房的视频数据。 X射线照射部将第四能谱和第五能量谱的X射线照射到与第一区域不同的乳房的第三区域。

    영상 획득 장치 및 그 방법과 영상 처리 장치 및 그 방법
    84.
    发明公开
    영상 획득 장치 및 그 방법과 영상 처리 장치 및 그 방법 有权
    用于获取图像的装置和方法以及处理图像的装置和方法

    公开(公告)号:KR1020090080616A

    公开(公告)日:2009-07-27

    申请号:KR1020080006478

    申请日:2008-01-22

    Abstract: An image acquisition apparatus and method and an image processing apparatus and method are provided to recover a clear color image by using a hand-shaking function, thereby being usefully applied to night watch photographing, night monitoring photographing, and indoor performance photographing. A sensing unit(110) senses a pixel array value by using a color filter. The color filter comprises a color pixel and a reference pixel. The color pixel is to obtain a color image. The reference pixel is to obtain a reference frame used for hand-shaking function estimation. An exposure controller(120) controls an exposure time for the reference pixel and the color pixel. A video generator(130) generates a long-exposure color video signal and a short-exposure reference video signal which are mutually arranged from the sensed pixel array value.

    Abstract translation: 提供了一种图像获取装置和方法以及图像处理装置和方法,以便通过使用握手功能恢复清晰的彩色图像,从而有效地应用于夜间拍摄,夜间监视拍摄和室内表演拍摄。 感测单元(110)通过使用滤色器来感测像素阵列值。 滤色器包括彩色像素和参考像素。 彩色像素是获得彩色图像。 参考像素是获得用于握手功能估计的参考帧。 曝光控制器(120)控制参考像素和彩色像素的曝光时间。 视频发生器(130)产生从感测的像素阵列值相互排列的长曝光彩色视频信号和短曝光参考视频信号。

    반도체 메모리 시스템 및 그것의 액세스 방법
    85.
    发明公开
    반도체 메모리 시스템 및 그것의 액세스 방법 有权
    半导体存储器系统及其访问方法

    公开(公告)号:KR1020090066680A

    公开(公告)日:2009-06-24

    申请号:KR1020070134342

    申请日:2007-12-20

    CPC classification number: G11C16/20 G11C16/10 G11C11/5628 G11C16/30

    Abstract: A semiconductor memory system and its accessing method are provided, which improve the reliability of the semiconductor memory system by performing the access considering the change of the cell characteristic. A semiconductor memory system(100) comprises the nonvolatile memory(110) and memory controller(120). The nonvolatile memory stores monitoring data among a plurality of memory cells in one or more memory cells. The memory controller controls the nonvolatile memory. The memory controller detects monitoring data. The memory controller controls the bias voltage provided to a plurality of memory cells according to the detected result.

    Abstract translation: 提供一种半导体存储器系统及其访问方法,其通过考虑到单元特性的改变来执行访问来提高半导体存储器系统的可靠性。 半导体存储器系统(100)包括非易失性存储器(110)和存储器控制器(120)。 非易失性存储器存储一个或多个存储单元中的多个存储单元之间的监视数据。 存储器控制器控制非易失性存储器。 内存控制器检测监控数据。 存储器控制器根据检测结果控制提供给多个存储单元的偏置电压。

    멀티-비트 플래시 메모리 장치 및 그것의 프로그램 및 읽기방법
    86.
    发明公开
    멀티-비트 플래시 메모리 장치 및 그것의 프로그램 및 읽기방법 有权
    多位闪存存储器件及其程序及其读取方法

    公开(公告)号:KR1020090041157A

    公开(公告)日:2009-04-28

    申请号:KR1020070106724

    申请日:2007-10-23

    Abstract: A multi-bit flash memory device and a program and read methods thereof is provided to perform reading operation accurately by controlling the reading operation according to the programming state of multi-bit data. A memory cell array(110) stores the N- bit data, and a control circuit(150) controls all operations related to program, reading, and erasing of a flash memory(100). Data to be programmed is loaded the control circuit through a buffer in a reading circuit(130). The control circuit applies a program voltage, a pass voltage, and 0V to a selected word line, non-selected word line, and a bulk by controlling a decoding circuit(120), voltage generation circuit(160), and writing/reading circuit.

    Abstract translation: 提供多位闪存器件及其程序及其读取方法,以通过根据多位数据的编程状态控制读取操作来精确地执行读取操作。 存储单元阵列(110)存储N位数据,并且控制电路(150)控制与闪速存储器(100)的程序,读取和擦除相关的所有操作。 要编程的数据通过读取电路(130)中的缓冲器加载控制电路。 控制电路通过控制解码电路(120),电压产生电路(160)以及写入/读取电路(160)向所选择的字线,未选字线和批量施加编程电压,通过电压和0V 。

    플래시 메모리 시스템 및 그것의 에러 정정 방법
    87.
    发明公开
    플래시 메모리 시스템 및 그것의 에러 정정 방법 有权
    闪存存储器系统及其错误校正方法

    公开(公告)号:KR1020090005549A

    公开(公告)日:2009-01-14

    申请号:KR1020070068681

    申请日:2007-07-09

    Abstract: A flash memory system and an error correction method thereof are provided to reduce the load of an error correction circuit and improve the performance of the error correction circuit. An error correction circuit(230) generates an error correction code for correcting a bit error from the data transmitted to a paper buffer circuit(130) through a row selection circuit(140) when operating a software. The generated error correction code is transferred to the paper buffer circuit through the row selection circuit, and the paper buffer circuit includes a main region and a spare region. The main region stores the data to be programmed and the spare region stores an error correction code. The error correction circuit receives data and an error correction code from the paper buffer circuit during reading operation, and detects whether or not the transmitted data have an error by using the error correction code.

    Abstract translation: 提供一种闪存系统及其纠错方法,以减少误差校正电路的负载并提高纠错电路的性能。 误差校正电路(230)在操作软件时,通过行选择电路(140)产生用于校正通过行选择电路(140)发送到纸张缓冲电路(130)的数据的位错误的纠错码。 生成的纠错码通过行选择电路传送到纸张缓冲电路,纸缓冲电路包括主区域和备用区域。 主区域存储要编程的数据,备用区域存储纠错码。 误差校正电路在读取操作期间从纸张缓冲器电路接收数据和纠错码,并且通过使用纠错码来检测发送的数据是否具有错误。

    비휘발성 메모리의 멀티 비트 프로그래밍 장치 및 방법
    88.
    发明授权
    비휘발성 메모리의 멀티 비트 프로그래밍 장치 및 방법 有权
    비휘발성메모리의멀티비트프로그래밍장치및방법

    公开(公告)号:KR100873825B1

    公开(公告)日:2008-12-15

    申请号:KR1020070042764

    申请日:2007-05-02

    CPC classification number: G11C11/5628 G11C2211/5621 G11C2211/5641

    Abstract: A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells.

    Abstract translation: 提供了一种用于非易失性存储器的多位编程设备和方法。 在一个示例实施例中,多位编程设备可以包括:多位编程单元,被配置为将编程原始多位数据多位编码到存储器单元阵列中的目标存储器单元;备份编程单元,被配置为选择备份 存储器单元阵列中的存储器单元相对于原始多位数据的每一位,并且将原始多位数据的每一位编程到所选择的备份存储器单元中的相应一个。

    프로그래밍 특성을 이용한 멀티 비트 프로그래밍 장치 및방법
    89.
    发明公开
    프로그래밍 특성을 이용한 멀티 비트 프로그래밍 장치 및방법 无效
    使用APARATUS使用编程特性和方法的多位编程技术

    公开(公告)号:KR1020080096210A

    公开(公告)日:2008-10-30

    申请号:KR1020070041372

    申请日:2007-04-27

    CPC classification number: G11C16/34 G06F9/461 G11C16/10

    Abstract: A multi-bit programming apparatus and method are provided to reduce errors considerably in a process for grasping programming characteristics of a memory, and shorten the time taken for multi-bit programming. A programming characteristic detection unit(210) detects each programming characteristic of memory cells in a target memory page during a process of multi-bit programming original data within the target memory page. A backup programming part(220) selects a backup memory page within a memory cell array and backup-programs information about the detected programming characteristics in the backup memory page. A multi-bit programming control part(230) controls a multi-bit programming process by using information about the programming characteristics backup-programmed.

    Abstract translation: 提供了一种多位编程装置和方法,用于在用于掌握存储器的编程特性的过程中显着减少误差,并缩短了多位编程所需的时间。 编程特性检测单元(210)在目标存储器页面内的多位编程原始数据的处理期间检测目标存储器页面中的存储器单元的编程特性。 备份编程部分(220)选择存储器单元阵列内的备份存储器页面,并且在备份存储器页面中备份关于检测到的编程特性的信息。 多位编程控制部件(230)通过使用关于备份编程的编程特性的信息来控制多位编程处理。

    초기 독출 동작없이 메모리 셀에 데이터를 프로그래밍할 수있는 메모리 셀 프로그래밍 방법 및 반도체 메모리 장치
    90.
    发明公开
    초기 독출 동작없이 메모리 셀에 데이터를 프로그래밍할 수있는 메모리 셀 프로그래밍 방법 및 반도체 메모리 장치 失效
    存储器编程方法和半导体存储器件,能够在没有初始读操作的情况下在存储器单元中编程数据

    公开(公告)号:KR1020080069479A

    公开(公告)日:2008-07-28

    申请号:KR1020070007246

    申请日:2007-01-23

    Inventor: 강동구

    Abstract: A memory cell programming method and a semiconductor memory device are provided to reduce memory cell programming time by programming data in a memory cell without initial read operation. At least one memory cell stores data of n bits. A first or an n-th latch(LAT1-LATn) receives the data and then latches the data. The k-th latch receives and latches k-th bit of the data, and programs the k-th bit latched in the k-th latch into the memory cell, by referring to the first or the (k-1)th bit latched in the first or the (k-1)th latch. The latch is included in a page buffer of a semiconductor memory device(500).

    Abstract translation: 提供存储单元编程方法和半导体存储器件以通过在存储单元中编程数据而不进行初始读取操作来减少存储单元编程时间。 至少一个存储单元存储n位的数据。 第一个或第n个锁存器(LAT1-LATn)接收数据,然后锁存数据。 第k个锁存器接收并锁存数据的第k位,并且通过参考被锁存的第(k-1)位来将锁存在第k个锁存器中的第k位编程到存储器单元中 在第一或第(k-1)个锁存器中。 锁存器包括在半导体存储器件(500)的页缓冲器中。

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