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公开(公告)号：KR100630705B1
公开(公告)日：2006-10-02
申请号：KR1020040083971
申请日：2004-10-20
Applicant: 삼성전자주식회사
IPC: H01L27/146 , H01L23/00
CPC classification number: H04N5/2254 , H01L31/0203 , H01L31/02325 , H01L2224/48091 , H04N5/2253 , H01L2924/00014
Abstract: In one embodiment, a camera module includes a lens holder and a flexible printed circuit board, both directly attachable on an image recognition chip without using a PCB. Thus, cost can be reduced by at least the price of the PCB. Also, a size of the camera module can be reduced. A method of fabricating the camera module of embodiments of the present invention can exclude chip attaching and wire bonding processes. Thus, the camera module can be fabricated within a short time using a simple assembling process.
Abstract translation: 在一个实施例中，相机模块包括透镜保持器和柔性印刷电路板，两者可以直接连接在图像识别芯片上而不使用PCB。 因此，PCB的价格至少可以降低成本。 此外，可以减小相机模块的尺寸。 制造本发明的实施例的相机模块的方法可以排除芯片附接和引线接合过程。 因此，可以使用简单的组装过程在短时间内制造相机模块。
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公开(公告)号：KR100585143B1
公开(公告)日：2006-05-30
申请号：KR1020040033377
申请日：2004-05-12
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/16 , H01L23/49572 , H01L2224/13099 , H01L2224/16225 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12044
Abstract: 열에 의하여 베이스 필름이 변형되는 것을 방지하는 반도체 칩이 탑재된 탭방식의 패키지 및 그 제조방법에 대해 개시한다. 개시된 패키지 및 제조방법은 베이스 필름 상에 형성되어 반도체 칩과 연결되기 위한 복수 개의 내부리드 및 반도체 칩의 네 모퉁이에 반도체 칩의 짧은 모서리에 수직하도록 반도체 칩의 네 모퉁이에 부착된 복수 개의 보강리드를 포함한다.
패키지, 탭, 내부리드, 보강리드-
公开(公告)号：KR1020060039613A
公开(公告)日：2006-05-09
申请号：KR1020040088783
申请日：2004-11-03
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L23/49816 , H01L23/13 , H01L23/5384 , H01L24/45 , H01L24/48 , H01L24/81 , H01L24/90 , H01L2224/11334 , H01L2224/13144 , H01L2224/16237 , H01L2224/451 , H01L2224/48227 , H01L2224/48228 , H01L2224/81201 , H01L2224/81203 , H01L2224/81205 , H01L2224/81801 , H01L2224/90 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H05K1/112 , H05K1/189 , H05K2201/0394 , H05K2201/09472 , H05K2201/10674 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2224/0401 , H01L2924/00012
Abstract: A chip-on-board (COB) package has a flip chip assembly structure and is used for an integrated circuit (IC) card. The COB package has conductive patterns as contact terminals on an outer surface of a non-conductive film, and an IC chip on an inner surface of the film. The film has a number of holes through which the conductive patterns are partly exposed. A number of conductive bumps on an active surface of the IC chip face the inner surface of the film and enter corresponding holes in the non-conductive film to mechanically join and electrically couple to the conductive patterns. The disclosed COB package and a related manufacturing method allow a reduction in production cost, simplified process, better electrical connections, and improved reliability.
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公开(公告)号：KR100539235B1
公开(公告)日：2005-12-27
申请号：KR1020030037861
申请日：2003-06-12
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: B23K1/0016 , B23K35/262 , B23K2201/40 , H01L23/49816 , H01L2224/73204
Abstract: A chip package including at least one interconnection lead, composed of at least one first metal, at least one bump, a surface of which is plated with at least one second metal with a melting point lower than the first metal, and a eutectic alloy, composed of the at least one first metal and the at least one second metal, that at least electrically connects the interconnection lead and the bump and a method of manufacturing a chip package.
Abstract translation: 1。一种芯片封装，包括至少一个互连引线和共晶合金，所述互连引线由至少一个第一金属，至少一个凸块和至少一个凸块构成，所述凸块的表面镀覆有至少一种熔点低于所述第一金属的第二金属， 由所述至少一个第一金属和所述至少一个第二金属构成，至少电连接所述互连引线和所述凸块以及制造芯片封装的方法。
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85.发明公开
公开(公告)号：KR1020050050919A
公开(公告)日：2005-06-01
申请号：KR1020030084582
申请日：2003-11-26
Applicant: 삼성전자주식회사
IPC: G02F1/1345
CPC classification number: G02F1/13452 , H01L23/4985 , H01L2224/16 , H05K3/222 , H05K3/361
Abstract: 입력패드를 2개의 상호 대향하는 양변에 나누어 배치하고, 바이패스 패턴을 칩 내부에 배선패턴 형태로 구비하며, 입·출력패턴이 칩 내부에 구비된 별도의 배선패턴에 의해 칩 내측에서 연결되도록 하여, 베이스 필름을 통과하는 회로패턴을 최소화시킨 구조의 게이트 TCP와, 상기 TCP에 실장되는 반도체 칩 그리고 상기 TCP가 적용된 액정표시장치가 제공된다.
이처럼, 반도체 칩과 베이스 필름에 형성되는 회로패턴들의 구조를 변경하여 게이트 TCP와 액정표시장치를 설계하면, 반도체 칩과 베이스 필름의 크기를 종래대비 줄일 수 있을 뿐 아니라 이로 인해 제조 비용을 절감할 수 있고, 또한 이를 채용할 경우 TCP와 액정표시장치의 소형화를 구현할 수 있게 된다.-
Patent Agency Ranking
公开(公告)号：KR1020040110296A
公开(公告)日：2004-12-31
申请号：KR1020030039525
申请日：2003-06-18
Applicant: 삼성전자주식회사
IPC: H01L27/146 , H01L23/00
CPC classification number: H04N5/2251 , H01L27/14618 , H01L27/14625 , H01L31/0203 , H01L31/02325 , H01L2224/16225 , H01L2924/00014 , H01L2224/0401
Abstract: PURPOSE: A semiconductor device for a solid-state imaging is provided to reduce a thickness and an area of the solid-state imaging semiconductor chip by laminating an aperture on the solid-state imaging semiconductor chip. CONSTITUTION: A semiconductor device for a solid-state imaging includes a lens attachment portion(15), a circuit board(110), a solid-state imaging semiconductor chip(40), and a first image processing semiconductor chip(60). The lens attachment portion contains a solid-state imaging lens. The circuit board includes a light receiving hole facing the solid-state imaging lens. The solid-state imaging semiconductor chip is electrically coupled with a lower portion of the circuit board and converts the signal from the light receiving hole to an image signal. The image processing semiconductor chip is formed not to block the light from the solid-state imaging lens and is fixed on a lower portion of the lens attachment portion. The image processing semiconductor chip is electrically coupled with an upper portion of the circuit board and processes the image signal.
Abstract translation: 目的：提供一种用于固态成像的半导体器件，用于通过在固态成像半导体芯片上层叠孔径来减小固态成像半导体芯片的厚度和面积。 构成：用于固态成像的半导体器件包括透镜安装部分（15），电路板（110），固态成像半导体芯片（40）和第一图像处理半导体芯片（60）。 透镜附着部分包含固态成像透镜。 电路板包括面对固态成像透镜的光接收孔。 固态成像半导体芯片与电路板的下部电耦合，并将来自光接收孔的信号转换为图像信号。 图像处理半导体芯片形成为不阻挡来自固态成像透镜的光并固定在透镜安装部的下部。 图像处理半导体芯片与电路板的上部电耦合并处理图像信号。
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公开(公告)号：KR1020040107060A
公开(公告)日：2004-12-20
申请号：KR1020030037861
申请日：2003-06-12
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: B23K1/0016 , B23K35/262 , B23K2201/40 , H01L23/49816 , H01L2224/73204
Abstract: PURPOSE: A package having a bonding between a gold plated lead and a gold bump and a manufacturing method thereof are provided to prevent a lead neck broken phenomenon by plating a gold layer on a connecting lead. CONSTITUTION: A package includes a connecting lead(200), a bump(110), and a bonding portion. The connecting lead is gold-plated. The bump includes a surface which has a metal layer plated thereon. The metal layer plated on the surface of the bump has a melting point lower than that of the gold layer plated on the connecting lead. The bonding electrically couples the lead and the bump by forming a eutectic alloy of the metallic layer having a low melting point and the gold layer. The metallic layer having a low melting point is a tin layer.
Abstract translation: 目的：提供具有镀金铅和金凸块之间的结合的封装及其制造方法，以通过在连接引线上镀金层来防止铅颈破损现象。 构成：包装包括连接引线（200），凸块（110）和接合部分。 连接引线镀金。 凸块包括其上镀有金属层的表面。 电镀在凸块表面上的金属层的熔点低于镀在连接引线上的金层的熔点。 通过形成具有低熔点的金属层和金层的共晶合金，该接合将引线和凸块电耦合。 具有低熔点的金属层是锡层。
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公开(公告)号：KR1020040092537A
公开(公告)日：2004-11-04
申请号：KR1020030026014
申请日：2003-04-24
Applicant: 삼성전자주식회사
IPC: H01L21/66
Abstract: PURPOSE: A tape wiring board for inspecting a semiconductor chip is provided to adapt easily to the increase of pins of the chip by improving the array of input test pads. CONSTITUTION: A window(312) for mounting a semiconductor chip(311) is formed at a center portion of a base film(310). Printed wiring is formed at both sides of the window on the base film. Input printed wiring(331) is one side of the window and output printed wiring(332) is the other side. Input test pads(351,352) are formed into a plurality of columns on the input printed wiring. The first outer pads(361) are formed at the end of the input printed wiring. The second outer pads(363) are formed at the end of the output printed wiring.
Abstract translation: 目的：提供用于检查半导体芯片的胶带接线板，通过改善输入测试焊盘的阵列，轻松适应芯片引脚的增加。 构成：用于安装半导体芯片（311）的窗（312）形成在基膜（310）的中心部分。 印刷布线形成在底膜的窗口的两侧。 输入印刷线路（331）是窗口的一侧，输出印刷线路（332）是另一侧。 输入测试焊盘（351,352）在输入印刷线路上形成多列。 第一外部衬垫（361）形成在输入印刷线路的末端。 第二外垫（363）形成在输出印刷布线的末端。
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公开(公告)号：KR1020030063049A
公开(公告)日：2003-07-28
申请号：KR1020020003605
申请日：2002-01-22
Applicant: 삼성전자주식회사
IPC: H01L23/48
Abstract: PURPOSE: A package film including a slit for distributing stress is provided to maximize an area of the film occupied by a package by forming a slit with a small area on the film so that the stress generated in forming the package is eliminated. CONSTITUTION: Sprocket holes of a predetermined width are widthwise formed at both edges of the package film(21) at regular intervals. A plurality of patterns(23) are formed in the circumference of a semiconductor chip mount region in the center of a width direction. Two circular holes and slits(24) composed of incision lines connecting the circular holes are formed between the sprocket holes and between the plurality of patterns.
Abstract translation: 目的：提供包括用于分布应力的狭缝的包装膜，以通过在膜上形成具有小面积的狭缝来最大化由包装所占据的膜的面积，从而消除在形成包装中产生的应力。 构成：预定宽度的链轮孔以规则的间隔宽度地形成在包装膜（21）的两个边缘处。 在宽度方向的中心的半导体芯片安装区域的周围形成有多个图案（23）。 在链轮孔之间和多个图案之间形成有由连接圆形孔的切割线构成的两个圆形孔和狭缝（24）。
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公开(公告)号：KR102250997B1
公开(公告)日：2021-05-12
申请号：KR1020140053253
申请日：2014-05-02
Applicant: 삼성전자주식회사
Abstract: 반도체패키지는반도체칩, 상부구조물및 하부구조물을포함한다. 상부구조물은상기반도체칩의상부에위치한다. 상부구조물은제 1 열팽창계수를갖는다. 하부구조물은상기반도체칩의하부에위치한다. 하부구조물은상기제 1 열팽창계수이하인제 2 열팽창계수를갖는다. 따라서, 하부구조물보다상부구조물이상대적으로더 많이팽창하게되어, 반도체패키지가상부로볼록하게휘어지는것을억제할수 있다.
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