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公开(公告)号：KR1020000009099A
公开(公告)日：2000-02-15
申请号：KR1019980029291
申请日：1998-07-21
Applicant: 삼성전자주식회사
Inventor： 최정환
IPC: G11C29/00
CPC classification number: H03K5/1565
Abstract: PURPOSE: The data duty cycle correction method is provided to correct a data with unstable duty cycle to a data with 50% duty cycle using a duty cycle correction circuit. CONSTITUTION: The data duty cycle correction method comprises the steps of: inputting a clock signal by a clock corrector; generating a first duty cycle control signal and a second duty cycle control signal and a correcting internal clock signal, wherein the first duty cycle signal and the second duty cycle signal are in proportion to a duty cycle error of the clock signal, but ratios of duty cycle are not same; generating a first reference voltage by a first reference voltage generator; inputting the first reference voltage and the second duty cycle control signal by a second reference voltage generator; generating a second reference voltage by adding and amplifying the first reference voltage and the second duty cycle control signal in the second reference voltage generator; inputting a data and the second reference voltage and the internal clock signal by a data receiver; comparing and amplifying the data and the second reference voltage; and correcting the duty cycle of the data.
Abstract translation: 目的：提供数据占空比校正方法，使用占空比校正电路将具有不利占空比的数据校正为具有50％占空比的数据。 构成：数据占空比校正方法包括以下步骤：通过时钟校正器输入时钟信号; 产生第一占空比控制信号和第二占空比控制信号和校正内部时钟信号，其中第一占空比信号和第二占空比信号与时钟信号的占空比误差成比例，但占空比 周期不一样; 由第一参考电压发生器产生第一参考电压; 通过第二参考电压发生器输入第一参考电压和第二占空比控制信号; 通过在第二参考电压发生器中增加和放大第一参考电压和第二占空比控制信号来产生第二参考电压; 通过数据接收机输入数据和第二参考电压和内部时钟信号; 比较和放大数据和第二参考电压; 并修正数据的占空比。
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公开(公告)号：KR102238717B1
公开(公告)日：2021-04-09
申请号：KR1020140145663
申请日：2014-10-27
Applicant: 삼성전자주식회사
Inventor： 최정환
Abstract: 메모리시스템은메모리컨트롤러, 제1 메모리모듈및 제2 내지제k 메모리모듈들(k는 3 이상의자연수)을포함할수 있다. 상기제1 메모리모듈은제1 메모리버스를통하여상기메모리컨트롤러와직접적으로포인트-투-포인트방식으로연결되며제1 데이터를상기메모리컨트롤러와교환할수 있다. 상기제2 내지제k 메모리모듈들은제2 메모리버스를통하여상기제1 메모리모듈과멀티-드롭방식으로연결되며, 제2 데이터를상기제1 메모리모듈을통하여상기메모리컨트롤러와교환할수 있다.
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公开(公告)号：KR102237739B1
公开(公告)日：2021-04-08
申请号：KR1020190011863
申请日：2019-01-30
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: 삼차원수직셀 구조를갖는디램은메모리셀들을단위공정을반복하여수직으로적층한삼차원구조를갖는다. 메모리셀들은 N개의(N은 2 이상의자연수) 층으로서수직구현이가능하다. 삼차원디램은각 층별로커다란환형의커패시터가상응하는트랜지스터를둘러싸거나각 층별로많은수의작은커패시터들이상응하는트랜지스터의주위에환형으로배치됨으로써디램의삼차원수직구조를효율적으로구현할수 있다.
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公开(公告)号：KR102210999B1
公开(公告)日：2021-02-03
申请号：KR1020167004569
申请日：2014-08-14
Applicant: 삼성전자주식회사
IPC: G06F3/0488 , G06F3/0482 , G06F3/0484 , G06F3/0481 , H04M1/725
Abstract: 터치스크린을포함하는디스플레이장치가적어도하나의애플리케이션을실행하는방법이개시된다. 본발명에따른애플리케이션실행방법은터치스크린상에포함된복수의영역각각에애플리케이션실행창을표시하는단계와, 복수의영역을구분하는적어도하나의경계선상에버튼을표시하는단계와, 버튼을선택하는입력을수신하는단계및 수신된입력에기초하여, 복수의영역중 소정의영역에서실행되는적어도하나의애플리케이션의목록을소정의영역에표시하는단계를포함할수 있다.
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Patent Agency Ranking
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公开(公告)号：KR1020140073398A
公开(公告)日：2014-06-16
申请号：KR1020130094070
申请日：2013-08-08
Applicant: 삼성전자주식회사
CPC classification number: G06F3/0488 , G06F3/0412 , G06F3/0416 , G06F3/0481 , G06F3/04845 , G06F3/14 , G06F3/1407 , G06F9/44 , G06F9/451 , G06F2203/04101 , G06F2203/04104 , G06F2203/04803 , G06F2203/04808 , G09G5/14 , G09G2354/00 , G06F3/041 , G06F3/0486 , G06F9/445
Abstract: Disclosed is a control method for a display device including a touchscreen. The control method according to the present invention includes the steps of displaying multiple windows which execute respective applications on a touchscreen so that the windows do not overlap each other; displaying a center button arranged on multiple edges separating the windows and the intersection points of the edges; receiving a window size modification command for changing the size of at least one window among the windows on the touchscreen; and changing the sizes of at the one or more windows among the windows, in response to the window size modification command, and displaying the window of the modified size.
Abstract translation: 公开了一种包括触摸屏的显示装置的控制方法。 根据本发明的控制方法包括以下步骤：在触摸屏上显示执行相应应用的多个窗口，使得窗口不彼此重叠; 显示分配窗口和边缘的交点的多个边缘上布置的中心按钮; 接收用于改变触摸屏上的窗口中的至少一个窗口的大小的窗口大小修改命令; 以及响应于所述窗口大小修改命令，改变所述窗口中的所述一个或多个窗口的大小，以及显示修改的大小的窗口。
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公开(公告)号：KR1020140070318A
公开(公告)日：2014-06-10
申请号：KR1020130037874
申请日：2013-04-08
Applicant: 삼성전자주식회사
CPC classification number: G11C7/10 , G11C5/04 , G11C7/22 , G11C2207/105 , G11C2207/2272
Abstract: A memory module includes multiple data ports and multiple memory devices. The data ports transceive corresponding data respectively. The memory devices include memory devices of a first set belonging to at least one rank directly connected to a corresponding data port among the data ports and memory devices of a second set belonging to at least another rank connected to the data port by passing via a corresponding memory device among the memory devices of the first set. Each of the memory devices of the first set responses to at least one chip selection signals to provide magnetic data from its memory core and at least one of other data from a memory core of one of the memory devices of the second set to the data port as the corresponding data.
Abstract translation: 存储器模块包括多个数据端口和多个存储器件。 数据端口分别收发相应的数据。 存储装置包括属于至少一个等级的至少一个等级的存储装置，该至少一个等级直接连接到数据端口中的对应数据端口，以及属于至少另一个等级的第二集合的存储装置，该第二集合通过相应的 存储器件在第一组的存储器件中。 第一组的每个存储器件响应于至少一个芯片选择信号，以从其存储器核心提供磁数据，以及从第二组的存储器件之一的存储器核心到数据端口的至少一个数据 作为相应的数据。
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公开(公告)号：KR1020130086887A
公开(公告)日：2013-08-05
申请号：KR1020120007981
申请日：2012-01-26
Applicant: 삼성전자주식회사
CPC classification number: G06F11/1048 , H03M13/356 , H03M13/3707
Abstract: PURPOSE: A memory buffer, devices including the same, and a data processing method thereof are provided to improve error detection and correction abilities by detecting and correcting errors in the memory buffer using an ECC algorithm. CONSTITUTION: An ECC algorithm selector selects one of ECC algorithms. An ECC logic circuit (530) generates ECC data by using the selected ECC algorithm. A first selector (521) transmits first data outputted from the outside to the ECC logic circuit or transmits first ECC data outputted from the ECC logic circuit to the outside in response to a selection signal. A second selector (523) transmits second ECC data outputted from the ECC logic circuit to a semiconductor memory device or transmits second data inputted from the semiconductor memory device to the ECC logic circuit in response to the selection signal.
Abstract translation: 目的：提供存储器缓冲器，包括其的装置及其数据处理方法，以通过使用ECC算法检测和校正存储器缓冲器中的错误来提高错误检测和校正能力。 构成：ECC算法选择器选择ECC算法之一。 ECC逻辑电路（530）通过使用选择的ECC算法生成ECC数据。 第一选择器（521）将从外部输出的第一数据发送到ECC逻辑电路，或者响应于选择信号将从ECC逻辑电路输出的第一ECC数据发送到外部。 第二选择器（523）将从ECC逻辑电路输出的第二ECC数据发送到半导体存储器件，或者响应于选择信号将从半导体存储器件输入的第二数据发送到ECC逻辑电路。
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公开(公告)号：KR1020130054094A
公开(公告)日：2013-05-24
申请号：KR1020110145015
申请日：2011-12-28
Applicant: 삼성전자주식회사
Abstract: PURPOSE: An antenna device is provided to arrange more than two coils in an antenna rod, thereby implementing electric field distribution similar to a 1/4 wavelength monopole with the length of a 1/16 wavelength. CONSTITUTION: A power supplying rod unit(112) is connected to a power supplying unit. A terminal rod unit(116) is formed in a terminal part separated from the power supplying rod unit. More than one middle rod unit(114) is formed between the power supplying rod unit and the terminal rod unit. A first helical unit(122) is formed between the power supplying rod unit and the middle rod unit. A second helical unit(124) is formed between the middle rod unit and the terminal rod unit.
Abstract translation: 目的：提供一种天线装置，用于在天线杆中布置多于两个的线圈，从而实现类似于长度为1/16波长的1/4波长单极的电场分布。 构成：供电单元（112）连接到供电单元。 端子棒单元（116）形成在与供电棒单元分离的端子部中。 在供电杆单元和端子杆单元之间形成有多于一个的中间杆单元（114）。 第一螺旋单元（122）形成在供电杆单元和中间杆单元之间。 第二螺旋单元（124）形成在中间杆单元和端子杆单元之间。
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