公开(公告)号：WO1985002818A1

公开(公告)日：1985-07-04

申请号：PCT/US1984001710

申请日：1984-10-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BAYMAN, Atiye ,  THOMAS, Mammen

IPC: B44C01/22

CPC classification number: H01L21/3065

Abstract: A plasma etching composition which comprises chlorine in an amount from about 40% to about 90%, a shape modifier species in an amount from about 10% to about 60%, and an etching selectivity enhancer in an amount sufficient to render the composition at least about 10 times as effective for etching a wafer as for etching a masking layer, the above percents being by mole. The composition is useful for plasma etching of a semiconductor wafer, (10) masked with a masking layer (12) having an opening (20) therethrough exposing a portion of the wafer (10) which is to be etched in order to form a depression (24) of a desired depth. This allows depressions of increased depth to be formed in wafers without increasing the thickness of the masking layer.

公开(公告)号：WO1985002306A1

公开(公告)日：1985-05-23

申请号：PCT/US1984001712

申请日：1984-10-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  VARADARAJAN, Hemmige, D.

IPC: H03K19/086

CPC classification number: H03K19/0136 ,  H03K19/086 ,  H03K19/0866

Abstract: A dynamic ECL circuit (Figs. 2-5) which drives loads (17, 18) having significant capacitance. The dynamic ECL circuit may utilize single level (Figs. 2-4) or multiple level logic (Fig. 5) and may be configured, for example, as an OR/NOR gate. A capacitor (C1, C2) is placed between the base of a current source transistor (10, 11) and a circuit point having a logic level complementary to the output (30, 31) connected to the current source. As logic transitions occur within the circuit and are presented on the output, a transient current will be experienced through the capacitor due to the shift in the complementary level thereby momentarily alterning the voltage on the base of the current source transistor. The dynamic alteration of base voltage produces a momentary change in the current through the current source transistor which serves to both speed up the high-to-low transition time and the low-to-high transition time on the output line.

公开(公告)号：WO1985002304A1

公开(公告)日：1985-05-23

申请号：PCT/US1984001790

申请日：1984-11-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  VARADARAJAN, Hemmige, D.

IPC: H03F01/30

CPC classification number: H03K19/086 ,  G05F3/225 ,  H03K19/0866

Abstract: A bias circuit which tracks the gain and operating characteristics of other transistors in an integrated circuit. The bias circuit employs the bandgap reference voltage, VCS, as the power source. By a transistor (26) and resistor network (24, 28, 29) a bias circuit voltage (VCSL) is generated. The bias circuit is useful in providing a bias to the base (e) of a dynamically switchable low drop current source (33) useful in ECL circuits.

Abstract translation: 跟踪集成电路中其他晶体管的增益和工作特性的偏置电路。 偏置电路采用带隙参考电压VCS作为电源。 通过晶体管（26）和电阻网络（24,28,29）产生偏置电路电压（VCSL）。 偏置电路对于在ECL电路中有用的可动态切换的低压降电流源（33）的基极（e）提供偏置是有用的。

公开(公告)号：WO1985000686A1

公开(公告)日：1985-02-14

申请号：PCT/US1984001177

申请日：1984-07-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WANG, Bu-Chin ,  NARAYAN, Shankar, S.

IPC: G10L01/00

CPC classification number: H04B1/667 ,  G10L25/27

Abstract: Apparatus for coding (Fig. 2A) an original speech signal having a waveform, including a waveform coder (14) operative at a low bit rate, for waveform coding the original speech signal to produce a coded signal having distortion, and an adaptive spectral shaping filter (80, 84) for filtering the distortion in the speech signal. The waveform coder has waveform coding data and the filter has filter coefficient data that are used by a decoding apparatus (Fig. 2B) to reconstruct the original speech signal. Also disclosed are various embodiments of speech analyzers and speech synthesizers which are implemented based on the coding and decoding principles of the coding decoding apparatus.

Abstract translation: 用于编码（图2A）具有波形的原始语音信号的装置，包括以低比特率工作的波形编码器（14），用于对原始语音信号进行波形编码，以产生具有失真的编码信号，以及自适应频谱整形 滤波器（80,84），用于滤除语音信号中的失真。 波形编码器具有波形编码数据，并且滤波器具有由解码装置（图2B）使用的滤波器系数数据，以重构原始语音信号。 还公开了基于编码解码装置的编码和解码原理实现的语音分析器和语音合成器的各种实施例。

公开(公告)号：WO1983001166A1

公开(公告)日：1983-03-31

申请号：PCT/US1982001008

申请日：1982-07-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  STAUFFER, Michael, K.

IPC: H04L27/10

CPC classification number: H04L27/10

Abstract: Un modulateur-démodulateur (modem) asynchrone à modulation par déplacement de fréquences pouvant fonctionner à des vitesses de transmission de données de 300, 600 et 1200 bits par seconde dans un canal téléphonique à fréquence vocale est compatible avec les spécifications des types de modems Bell 103/113, Bell 202, CCITT V.21 et CCITT V.23. Selon l'invention le modem est incorporé dans un seul circuit intégré de manière à réduire au minimum les composants extérieurs d'un système. Le modem est programmable par broche, c'est-à-dire, le mode et la vitesse de fonctionnement sont définis par un signal parallèle de données numériques appliquées aux terminaux du dispositif. Des techniques de traitement de signaux numériques sont utilisées pour exécuter toutes les fonctions principales, y compris la modulation (32, 44) et le filtrage (30, 46). Des fonctions de multiplication sont exécutées sans multiplicateur en utilisant des registres à décalage (62, 68, 114) et une arithmétique de signes canoniques (64, 66). Des circuits de conversion analogique/numérique (28) et numérique/analogique (48) sontincorporés dans le dispositif.

公开(公告)号：WO1998023069A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021467

申请日：1997-11-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  JANESCH, Stephen, T. ,  HENDRICKSON, Alan ,  SCHNIZLEIN, Paul

IPC: H04L27/227

CPC classification number: H04L27/2275 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

Abstract: A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal. In one embodiment of the phase detector, the logic unit analyzes the signs of the two digital signals and then accordingly adds or subtracts the I and Q signals to generate the phase-error signal. In another embodiment, the logic unit determines the magnitude of the phase-error signal by finding the difference in magnitudes of the two digital signals and constructing a phase-error signal proportional to this difference. The logic unit then determines the sign of the phase-error signal by analyzing the signs of the I and Q digital signals. The logic unit thus uses simple arithmetic operations to generate the phase-error signal, thereby reducing the complexity and cost of the phase detector.

Abstract translation: 一种使用简单的算术运算来测量DQPSK数字通信接收机的载波恢复机制中的相位误差的相位检测器。 载波恢复机制是提供通信系统的发射机和接收机中的振荡器之间的同步的反馈回路; 相位检测器测量与该同步的偏差，并产生在反馈回路中使用的相位误差信号以使振荡器同步。 为了执行该测量，相位检测器将接收的信号作为输入，并将其与接收机中的本地振荡器进行比较，以产生两个数字信号：接收信号的同相（I）和正交相位（Q）分量。 这些信号是逻辑单元的输入，它使用这两个信号来确定相位误差信号。 在相位检测器的一个实施例中，逻辑单元分析两个数字信号的符号，然后相应地增加或减少I和Q信号以产生相位误差信号。 在另一个实施例中，逻辑单元通过找到两个数字信号的幅度差并构造与该差成比例的相位误差信号来确定相位误差信号的大小。 逻辑单元然后通过分析I和Q数字信号的符号来确定相位误差信号的符号。 因此，逻辑单元使用简单的算术运算来产生相位误差信号，从而降低了相位检测器的复杂性和成本。

公开(公告)号：WO1998018292A1

公开(公告)日：1998-04-30

申请号：PCT/US1997019478

申请日：1997-10-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GULICK, Dale, E.

IPC: H04R03/00

CPC classification number: H04R3/00

Abstract: There is provided a novel powered loudspeaker implemented to be compatible with the USB specification. The powered speaker includes a speaker driven by a power amplifier coupled to a power supply. Both the amplifier and the power supply, in turn, are coupled to a USB controller. The controller is configured to provide USB functionality and compatibility. In addition, it provides a phase locked loop (PLL) for recovering a timer clock from the received data stream. The present invention further includes a function whereby the absence of data on the relevant channel is detected and the output to the speakers is muted in response thereto. A further circuit is provided that controls when the output to the speaker is turned on such that no clicks or pops occur at power-up or when the device or bus is not stable. In addition, tone control, including base and treble filters, volume control, and balance between left and right outputs (in a stereo version) are provided. Furthermore, power management functionality is provided. If the USB has been idle for a predetermined period of time, the system can place itself into a low power sleep mode, or the loudspeaker can be placed into a sleep mode via software from the host.

Abstract translation: 提供了一种实现与USB规范兼容的新型有源扬声器。 有源扬声器包括由耦合到电源的功率放大器驱动的扬声器。 放大器和电源又连接到USB控制器。 控制器配置为提供USB功能和兼容性。 另外，它提供了一种用于从接收到的数据流中恢复定时器时钟的锁相环（PLL）。 本发明还包括一个功能，其中检测到相关信道上的数据不存在，并且响应于此扬声器的输出被静音。 提供另一电路，用于控制扬声器的输出何时被接通，使得在上电时或当设备或总线不稳定时不会发生点击或咔嗒声。 此外，还提供了音调控制，包括基本和高音滤波器，音量控制以及左右输出之间的平衡（立体声版本）。 此外，还提供电源管理功能。 如果USB已经空闲了预定的时间段，则系统可以将自己置于低功率睡眠模式，或者可以通过来自主机的软件将扬声器置于睡眠模式。

公开(公告)号：WO1998018080A1

公开(公告)日：1998-04-30

申请号：PCT/US1997019059

申请日：1997-10-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HELMS, Frank, P.

IPC: G06F13/40

CPC classification number: G06F13/4063 ,  G06F13/4068

Abstract: A Peripheral Component Interconnect (PCI) compatible peripheral device for coupling to a PCI bus, the peripheral device comprising a primary function component and a connection portion. The primary function includes a PCI interface for coupling to the PCI bus, and a primary configuration space coupled to the PCI interface and accessible by the PCI bus via the PCI interface. The connection portion is coupled to the primary function component and supports a secondary function component. The primary function component provides PCI bus access via the PCI interface to the secondary function component when the secondary function component is coupled to the connection portion. The primary function component provides PCI bus access via the PCI interface to a secondary configuration space when the secondary function component is coupled to the connection portion.

Abstract translation: 一种用于耦合到PCI总线的外围组件互连（PCI）兼容的外围设备，所述外围设备包括主要功能部件和连接部分。 主要功能包括用于耦合到PCI总线的PCI接口和耦合到PCI接口的主要配置空间，并可通过PCI接口由PCI总线访问。 连接部分耦合到主要功能部件并且支持辅助功能部件。 当辅助功能组件耦合到连接部分时，主要功能部件通过PCI接口将PCI总线接入辅助功能组件。 当辅助功能组件耦合到连接部分时，主要功能部件通过PCI接口将PCI总线访问提供给辅助配置空间。

公开(公告)号：WO1998014955A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017552

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  WENDELL, Dennis, L.

IPC: G11C29/00

CPC classification number: G11C29/026 ,  G06F12/1054 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A manufacturing defect which causes a memory cell load device to be non-functional is frequently difficult to test. Such a defective memory cell can be written and subsequently read successfully even without the missing load device. But if the delay between the write and the subsequent read is long enough, the internal node of the memory cell leaks down to a degraded high level, and only then will the memory cell fail. The delay required to detect such a failure may easily reach tens of seconds, which is entirely inconsistent with the required economies of manufacturing test. A data retention circuit and method allows high speed test of a static memory cell to ensure that the load devices within the cell are actually present and functioning. An analog word line drive capability allows the active word line to be driven to a user-controllable analog level. This is accomplished by connecting the "VDD" and N-well of the final PMOS stage of the row decoder to an isolated terminal which is normally connected to VDD when assembled , but which is independently available prior to packaging. By lowering the analog word line voltage compared to the memory array power supply voltage, a written high level in a memory cell lacking a load device is not pulled high (because the load device in question is missing) and is already low enough to cause a subsequent read to immediately fail. Consequently, the memory array can be tested without requiring long delays between the write and read of each memory cell. Advantageously, the row and column support circuits and sensing circuits operate at the normal power supply levels for which they were designed and which may be independently margin tested.

Abstract translation: 导致存储单元负载装置不起作用的制造缺陷常常难以测试。 这样一个有缺陷的存储器单元可以被写入并随后读取成功，即使没有丢失的负载设备。 但是如果写入和后续读取之间的延迟足够长，则内存单元的内部节点会泄漏到降级的高电平，只有存储单元才会失败。 检测到这种故障所需的延迟可能容易达到数十秒，这完全不符合制造测试的所需经济性。 数据保持电路和方法允许对静态存储器单元进行高速测试，以确保单元内的负载装置实际存在和运行。 模拟字线驱动能力允许有源字线被驱动到用户可控的模拟电平。 这通过将行解码器的最终PMOS级的“VDD”和N阱连接到组装时通常连接到VDD的隔离端子来实现，但是在封装之前可以独立使用。 通过降低与存储器阵列电源电压相比的模拟字线电压，在缺少负载装置的存储单元中写入的高电平不会被拉高（因为所讨论的负载装置丢失），并且已经足够低以致导致 后续阅读立即失败。 因此，可以测试存储器阵列，而不需要在每个存储器单元的写入和读取之间的长时间延迟。 有利地，行和列支持电路和感测电路在它们被设计的正常电源电平下工作，并且可以独立地进行裕度测试。

公开(公告)号：WO1998014944A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017668

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HOLST, John, Christian ,  DRAPER, Donald, A.

IPC: G11C05/14

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

Abstract translation: 有源电源滤波器使用电阻元件和耦合在节点处的电容元件以及由节点控制的具有控制端的开关有效地消除了电源噪声。 有源电源滤波器适用于高速微处理器的锁相环（PLL）中的压控振荡器（VCO）的高频操作。 有源电源滤波器消除了VCO噪声，否则会产生抖动，从而降低微处理器的有效时钟周期。 有源电源滤波器在除VCO，PLL和微处理器之外的应用中同样有用，其中从电源中去除大量噪声是有用的。