公开(公告)号：DE10034925A1

公开(公告)日：2002-01-31

申请号：DE10034925

申请日：2000-07-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT

IPC: G11C11/22 ,  G11C11/408 ,  G11C8/00

公开(公告)号：DE10006243A1

公开(公告)日：2001-08-23

申请号：DE10006243

申请日：2000-02-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER JOCHEN ,  FISCHER HELMUT

IPC: H01L23/525 ,  H01L27/10

Abstract: The invention relates to a fusible link configuration in or on integrated circuits, in particular highly integrated memory chips, in which in each case one bank of fusible links (F1, F2, . . . ), together with an evaluation logic unit is configured beside and in association with a memory field segment. The evaluation logic unit is electrically connected to the fusible links (F1, F2, . . . ) and determines whether one or more of the fusible links (F1, F2, . . . ) is severed. One or more banks of the fusible links (F1, F2, . . . ) are divided up into smaller units while restricting the width(s) of the bank or banks. The units are grouped such that at least some of the fusible links (F1, F2, . . . ) are located beside one another transversely with respect to the width direction of the bank.

公开(公告)号：DE19960557A1

公开(公告)日：2001-07-05

申请号：DE19960557

申请日：1999-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAETZ THORALF ,  FISCHER HELMUT

IPC: G11C11/407 ,  G11C11/4076

Abstract: The memory has memory cells in a matrix field (11) combined into addressable units of row and column lines, a decoder (40) for selecting a column line and connected to a selection line (20), a read amplifier (51) associated with all memory cells of a selected column line and a data signal line (30) for transferring an already amplified data signal of a cell in the selected column line. The read amplifier input is connected to the data signal line for further data signal processing and the decoder and read amplifier are arranged on the edge and on the opposite side of the memory cell field.

公开(公告)号：DE19960557B4

公开(公告)日：2006-09-07

申请号：DE19960557

申请日：1999-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRAETZ THORALF ,  FISCHER HELMUT

IPC: G11C11/407 ,  G11C11/4076

Abstract: An integrated dynamic semiconductor memory has memory cells which are provided in a matrix-like memory cell array and are combined to form units with column lines and row lines. The integrated dynamic semiconductor memory has a decoder for selecting one of the column lines and a sense amplifier which is jointly allocated to all the memory cells in a selected column line. The sense amplifier is connected to a data signal line for the purpose of further processing a data signal from an addressed memory cell. The decoder for selecting one of the column lines and the sense amplifier are provided at the edge and on opposite sides of the memory cell array. By separating the control for selection of the column lines and of the data output path, successive steps in the process of read access can be controlled in a self-adjusting manner by the respective preceding signal.

公开(公告)号：DE10109486B4

公开(公告)日：2006-01-05

申请号：DE10109486

申请日：2001-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SZCZYPINSKI KAZIMIERZ ,  FISCHER HELMUT ,  CHRYSOTOMIDES ATHANASIA

IPC: G11C7/06 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/108 ,  H03K3/356 ,  H03K17/687

Abstract: An integrated DRAM memory component has sense amplifiers which, respectively within the framework of the integrated component, are formed from a multiplicity of transistor structures, arranged regularly in cell arrays, and signal interconnect structures with amplification transistors for bit line signal amplification. The amplification transistors are of identical design and they lie opposite one another in pairs in adjacent transistor rows. Signal interconnects, which are associated with the transistor rows and run parallel thereto, supply actuation signals. The signal interconnects for the actuation signals have the same arrangement symmetry as the amplification transistors, which means that the amplification transistors in adjacent transistor rows are in the same signal interconnect proximity.

公开(公告)号：DE10324611A1

公开(公告)日：2004-12-30

申请号：DE10324611

申请日：2003-05-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： EGERER JENS ,  FISCHER HELMUT

IPC: G11C5/14 ,  G11C11/407 ,  G11C29/00 ,  G11C29/02 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

Abstract: An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block supply line and a block ground line, which supply individual switching elements of the subcircuit blocks with a voltage. Each block supply line and block ground line is connected to a chip supply line and a chip ground line, which run outside the area sections of the subcircuit blocks. At least one connection between the chip supply line and the block supply line of at least one subcircuit block or between the chip ground line and the block ground line of at least one subcircuit block can be isolated by a switching device. Furthermore, a method for reducing leakage currents in a semiconductor memory, which, depending on the operating state of the semiconductor memory, isolates or connects individual subcircuit blocks of the semiconductor memory from or to a voltage supply.

公开(公告)号：DE10234679A1

公开(公告)日：2004-02-19

申请号：DE10234679

申请日：2002-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SZCZYPINSKI KAZIMIERZ ,  FISCHER HELMUT

IPC: G11C8/00 ,  G11C8/06 ,  G11C11/408 ,  G11C8/12

Abstract: A memory device comprises a cell array of lines and gaps, an address receiver (214) with a connection by busses (232,234) to address latches (236,256) and a device (244) which only drives the line address busses if an activation signal is active. An Independent claim is also included for an operating process for the above device.

公开(公告)号：DE10149099B4

公开(公告)日：2004-02-12

申请号：DE10149099

申请日：2001-10-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEIFFER JOHANN ,  FISCHER HELMUT

IPC: G11C7/12 ,  G11C7/18 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/407

Abstract: A memory circuit contains areas having memory cells. To transfer memory data from/to the memory cells, two-wire local data lines are provided. Each of the local data lines is associated with one of the memory areas and is connected to a two-wire master data line, common to all the memory areas, by a line circuit-breaker. To represent the binary value of data on a local data line, the wires are driven, to first and second logic potentials. Each line circuit-breaker contains switching devices which, if one of the two wires in the local data line is at the second logic potential, autonomously transfer the potential to the associated wire in the master data line, and, if one of the two wires in the master data line is at the second logic potential, autonomously transfer the potential to the associated wire in the local data line.

公开(公告)号：DE10205196C2

公开(公告)日：2003-12-18

申请号：DE10205196

申请日：2002-02-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MORGAN ALAN ,  FISCHER HELMUT

IPC: G11C29/00

Abstract: An addressing device selects an element from a set of N regular elements or alternatively from a set of R

公开(公告)号：DE10146177C2

公开(公告)日：2003-12-11

申请号：DE10146177

申请日：2001-09-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MORGAN ALAN ,  FISCHER HELMUT

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/48 ,  H01L23/58 ,  H01L21/66

Abstract: Integrated circuits are tested on the wafer level through an additional circuit part that is electrically connected via at least one connecting line with the associated integrated circuit. The additional circuit part is integrated into an interspace between the integrated circuits of the wafer. Functions of the integrated circuit can be controlled via the connecting line. For example, in the case of a memory module such as a DRAM, internal voltages and/or currents of the integrated circuit can advantageously be measured even on internal lines which are otherwise only accessible with difficulty. Following the wafer-level testing and dicing of the integrated circuits into individual chips, the additional circuit part becomes unusable.