-
公开(公告)号:NO20052740A
公开(公告)日:2005-07-12
申请号:NO20052740
申请日:2005-06-08
Applicant: INTERDIGITAL TECH CORP
Inventor: KAZAKEVICH LEONID , OZLUTURK FATIH M , KEARNEY KENNETH P , HAQUE TANBIR , DEMIR ALPASLAN , NARAYAN GEETHA LAKSHMI
CPC classification number: H03G3/001 , H03D3/008 , H03D3/009 , H03G3/3068 , H03G3/3089 , H03G2201/103 , H03G2201/202 , H03G2201/302 , H03G2201/307 , H03G2201/508 , H04B1/30 , H04L2027/0016 , H04L2027/0024
-
公开(公告)号:NO20052740D0
公开(公告)日:2005-06-08
申请号:NO20052740
申请日:2005-06-08
Applicant: INTERDIGITAL TECH CORP
Inventor: KAZAKEVICH LEONID , OZLUTURK FATIH M , KEARNEY KENNETH P , HAQUE TANBIR , DEMIR ALPASLAN , NARAYAN GEETHA LAKSHMI
Abstract: In order to compensate for performance degradation caused by inferior low-cost analog radio component tolerances of an analog radio, a future system architecture (FSA) wireless communication transceiver employs numerous digital signal processing (DSP) techniques to compensate for deficiencies of such analog components so that modern specifications may be relaxed. Automatic gain control (AGC) functions are provided in the digital domain, so as to provide enhanced phase and amplitude compensation, as well as many other radio frequency (RF) parameters.
-
公开(公告)号:DE60327245D1
公开(公告)日:2009-05-28
申请号:DE60327245
申请日:2003-11-14
Applicant: INTERDIGITAL TECH CORP
Inventor: OZLUTURK FATIH , KAZAKEVICH LEONID , HAQUE TANBIR , DEMIR ALPASLAN , NARAYAN GEETHA LAKSHMI , KEARNEY KENNETH
Abstract: In order to compensate for performance degradation caused by inferior low-cost analog radio component tolerances of an analog radio, a future system architecture (FSA) wireless communication transceiver employs numerous digital signal processing (DSP) techniques to compensate for deficiencies of such analog components so that modern specifications may be relaxed. Automatic gain control (AGC) functions are provided in the digital domain, so as to provide enhanced phase and amplitude compensation, as well as many other radio frequency (RF) parameters.
-
公开(公告)号:DE60225861T2
公开(公告)日:2009-04-09
申请号:DE60225861
申请日:2002-02-04
Applicant: INTERDIGITAL TECH CORP
Inventor: DEMIR ALPASLAN , GRIECO DONALD M
Abstract: A method and an apparatus are disclosed for establishing a communication link between a user equipment (UE) and a base station in a wireless communication network. An incoming communication signal is sampled, wherein the sampling includes generating even and odd signal samples of the communication signal, a signal strength magnitude is approximated for each of the signal samples, and the signal strength magnitudes of the signal samples are accumulated. A peak sample is then identified, wherein the peak sample is the signal sample with a highest accumulated signal strength magnitude, an index value is assigned to the peak sample, wherein the index value indicates a chip location of a primary scrambling code, and a chip offset is assigned to the index value based on the index value. A code group number and slot offset is determined based on the chip offset, the primary scrambling code is retrieved based on the code group number and slot offset, and a search frequency of a UE is adjusted based on the primary scrambling code.
-
公开(公告)号:ES2304181T3
公开(公告)日:2008-09-16
申请号:ES06111667
申请日:2002-02-04
Applicant: INTERDIGITAL TECH CORP
Inventor: DEMIR ALPASLAN , GRIECO DONALD M
Abstract: Una unidad de equipo de usuario, UE, capaz de conducir una búsqueda de celda inicial y establecer un enlace de comunicación con una estación de base en una red de comunicación, de tal modo que el UE comprende: un primer módulo (12), configurado para procesar o tratar un código de sincronización primario de la señal de comunicación y asignar un valor de índice a una muestra de pico de dicha señal de comunicación, de tal modo que dicho valor de índice se utiliza para calcular un desajuste de chip de un código de mezcla criptográfica primario; un segundo módulo (14), configurado para utilizar el desajuste de chip calculado para detectar un número de grupo de código de mezcla criptográfica, un desajuste de ranura y un código de sincronización secundario de la señal de comunicación; un tercer módulo (16), configurado para recuperar un código de mezcla criptográfica primario de dicha señal de comunicación basándose en el desajuste de chip, en el número de grupo de código de mezcla criptográfica y en el desajuste de ranura; y un controlador (18), conectado a dicho primer módulo, a dicho segundo módulo y a dicho tercer módulo, y configurado para controlar un ajuste de una frecuencia de búsqueda en dicho UE con el fin de permitir que el tercer módulo recupere el código de mezcla criptográfica primario de dicha señal de comunicación, caracterizada por que dicho controlador (18) comprende adicionalmente: un primer registro de almacenamiento intermedio (13), configurado para almacenar códigos de mezcla criptográfica primarios rechazados; un segundo registro de almacenamiento intermedio (19), conectado al primer módulo (12) y configurado para almacenar vectores de desajuste de chip rechazados; un circuito lógico de decisión (2), configurado para determinar si el código de mezcla criptográfica detectado es correcto; y un circuito (6) de exclusión de ventana, conectado al primer registro de almacenamiento intermedio (13), al segundo registro de almacenamiento intermedio (9) y al circuito lógico de decisión (2), y configurado para detectar redes móviles terrestres públicas, PLMNs, para comprobar el código de mezcla criptográfica detectado frente a los códigos almacenados en dicho primer registro de almacenamiento intermedio (13), a fin de rechazar dicho código de mezcla criptográfica detectado si el código de mezcla criptográfica detectado se encuentra en el primer registro de almacenamiento intermedio (13) o se detecta una PLMN incorrecta, y superar un rechace causado por una PLMN incorrecta.
-
公开(公告)号:DE602004009579D1
公开(公告)日:2007-11-29
申请号:DE602004009579
申请日:2004-05-20
Applicant: INTERDIGITAL TECH CORP
Inventor: DEMIR ALPASLAN , KAZAKEVICH LEONID , HAQUE TANBIR
IPC: H03D3/00
Abstract: A digital baseband (DBB) radio frequency (RF) receiver includes a digital high pass filter compensation (HPFC) module used to suppress group delay variation distortion caused by using low cost analog high pass filters (HPFs) in the receiver. The digital HPFC module reduces a cutoff frequency, established by the HPFs for the real and imaginary signal component frequency domain responses by providing a first compensation signal having a first predetermined value (K 1 ). The digital HPFC module adjusts the gain of the high pass response of the real and imaginary signal component frequency domains by providing a second compensation signal having a second predetermined value (K 2 ).
-
公开(公告)号:MXPA06010997A
公开(公告)日:2007-01-25
申请号:MXPA06010997
申请日:2005-03-18
Applicant: INTERDIGITAL TECH CORP
Inventor: KAZAKEVICH LEONID , DEMIR ALPASLAN , HAQUE TANBIR , KLAHN GERALD
Abstract: Un metodo y aparato para ajustar dinamicamente la impedancia entre el amplificador de potencia (PA) y la antena del transmisor, para transferir eficientemente potencia desde el PA a la antena. La impedancia entre el PA y la antena se ajusta en base a las mediciones del nivel de potencia y/o mediciones de consumo de corriente directa (DC) del PA, dependiendo si el PA es un PA lineal o un PA de modo conmutado. En otra modalidad, en el transmisor se implementa un PA hibrido que incluye un PA lineal de primera etapa y un PA de modo conmutado de segunda etapa. El PA hibrido conecta selectivamente la salida del PA lineal de primera etapa a una de la entrada del PA de modo conmutado de segunda etapa y la salida del PA hibrido, dependiendo del nivel de potencia de salida del PA lineal de primera etapa, el nivel de potencia de salida del PA hibrido, o un requerimiento indicado por la orden de control de potencia de transmision (TPC).
-
公开(公告)号:CA2588262A1
公开(公告)日:2006-05-18
申请号:CA2588262
申请日:2005-11-02
Applicant: INTERDIGITAL TECH CORP
Inventor: STERNBERG GREGORY S , DEMIR ALPASLAN , PAN JUNG-LIN , LI BIN , YANG RUI , BELURI MIHAELA , PIETRASKI PHILIP J
Abstract: An adaptive equalizer including an equalizer filter and a tap coefficients generator used to process a sample data stream derived from a plurality of received signals is disclosed. The tap coefficients generator includes an equalizer tap update unit, a vector norm square estimator, an active taps mask generator, a switch and a pilot amplitude reference unit used to minimize the dynamic range of the equalizer filter. A dynamic mask vector is used to mask active taps generated by the equalizer tap update unit when an unmasked signal output by the equalizer filter is selected by the switch to generate an error signal fed to the equalizer tap update unit. A fixed mask vector is used to mask active taps generated by the equalizer tap update unit when a masked signal output by the equalizer filter is used to generate the error signal.
-
89.
公开(公告)号:CA2586992A1
公开(公告)日:2006-05-18
申请号:CA2586992
申请日:2005-10-19
Applicant: INTERDIGITAL TECH CORP
Inventor: DEMIR ALPASLAN , PIETRASKI PHILIP J , YANG RUI , BELURI MIHAELA
IPC: H03H7/40
Abstract: An apparatus for estimating and correcting baseband frequency error in a receiver is disclosed. An equalizer performs equalization on a sample data stream and generates filter tap values based on the equalization. An estimated frequency error signal is generated based on at least one of the filter tap values. A rotating phasor is generated based on the estimated frequency error signal. The rotating phasor signal is multiplied with the sample data stream to correct the frequency of the sample data stream. Alternatively, a channel estimator performs channel estimation and generates Rake receive finger weights based on at least one of the finger weights. An estimated frequency error signal is generated based on at least one of the finger weights.
-
公开(公告)号:NO20060057L
公开(公告)日:2006-02-01
申请号:NO20060057
申请日:2006-01-05
Applicant: INTERDIGITAL TECH CORP
Inventor: KAZAKEVICH LEONID , OZLUTURK FATIH M , DEMIR ALPASLAN , NARAYAN GEETHA LAKSHMI
Abstract: A digital baseband (DBB) receiver for receiving and processing a wireless communication signal. The DBB receiver includes at least one low noise amplifier (LNA), at least one demodulator, a direct current (DC) discharge circuit and an LNA control circuit. The LNA selectively amplifies the communication signal. The demodulator outputs analog real and imaginary signal components on real and imaginary signal paths, respectively, in response to receiving the communication signal from the LNA. The DC discharge circuit selectively discharges DC accumulating on at least one of the real and imaginary signal paths. The LNA control circuit turns the LNA on or off.
-
-
-
-
-
-
-
-
-