公开(公告)号：US11651896B2

公开(公告)日：2023-05-16

申请号：US17242327

申请日：2021-04-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung Wang ,  Hsih-Yang Chiu

IPC: H10B12/00 ,  H01L29/94 ,  H01G4/228 ,  H01G13/00 ,  H01L27/108

CPC classification number: H01G4/228 ,  H01G13/00 ,  H01L27/10829 ,  H01L27/10838 ,  H01L27/10861 ,  H01L29/945

Abstract: A capacitor structure is provided, which includes a contact layer, an insulating layer, a bottom conductive plate, a dielectric layer and a top conductive plate. The contact layer has first, second, third, fourth and fifth portions arranged from periphery to center. The insulating layer is disposed over the contact layer and has an opening exposing the contact layer. The bottom conductive plate is disposed in the opening and including first, second and third portions extending along a depth direction of the opening and separated from each other and in contact with the first, third and fifth portions of the contact layer, respectively. The dielectric layer is conformally disposed on the bottom conductive plate and in contact with the second and fourth portions of the contact layer. The top conductive plate is disposed on the dielectric layer. A method of manufacturing the capacitor is also provided.

公开(公告)号：US11456353B2

公开(公告)日：2022-09-27

申请号：US16930328

申请日：2020-07-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ting-Cih Kang ,  Hsih-Yang Chiu

IPC: H01L29/06 ,  H01L29/51 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.

公开(公告)号：US11456206B2

公开(公告)日：2022-09-27

申请号：US16936194

申请日：2020-07-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/768 ,  H01L23/528

Abstract: The present disclosure provides a semiconductor structure with a reduced pitch (half-pitch feature) and a method of manufacturing the same. The semiconductor structure includes a substrate, a dielectric layer, at least one main feature, at least one first conductive feature, at least one first spacer, a plurality of second conductive features, and a plurality of second spacers. The dielectric layer is disposed on the substrate. The main feature is disposed in the dielectric layer and contacting the substrate. The first conductive feature is disposed in the dielectric layer and on the main feature. The first spacer is interposed between the dielectric layer and a portion of the first conductive feature. The second conductive features are disposed in the dielectric layer and on either side of the first conductive feature. The second spacers are interposed between the dielectric layer and portions of the second conductive features.

公开(公告)号：US11270962B2

公开(公告)日：2022-03-08

申请号：US16665408

申请日：2019-10-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Pei-Jhen Wu ,  Ching-Hung Chang ,  Hsih-Yang Chiu

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor component, a re-routing layer, a bonding dielectric and an insulating layer. The re-routing layer is disposed over the semiconductor component and electrically coupled to the semiconductor component. The bonding dielectric is disposed over the semiconductor component to surround a top portion of the re-routing layer. The insulating layer is disposed between the semiconductor component and the bonding dielectric to surround a bottom portion of the re-routing layer.

公开(公告)号：US11217560B2

公开(公告)日：2022-01-04

申请号：US16665310

申请日：2019-10-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Pei-Jhen Wu ,  Ching-Hung Chang ,  Hsih-Yang Chiu

IPC: H01L25/065 ,  H01L23/00

Abstract: The present disclosure provides a die assembly. The die assembly includes a first die, a second die and a third die stacked together. The first die includes a plurality of first metal lines facing a plurality of second metal lines of the second die, and a second substrate beneath the second metal lines faces a plurality of third metal lines of the third die. The die assembly further includes at least one first plug, a first redistribution layer and a second redistribution layer. The first plug penetrates through the second substrate to connect to at least one of the second metal lines. A first redistribution layer physically connects at least one of the first metal lines to at least one of the second metal lines, and a second redistribution layer physically connects at least one of the third metal lines to the first plug.

公开(公告)号：US11121062B2

公开(公告)日：2021-09-14

申请号：US16211830

申请日：2018-12-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: The present disclosure relates to a semiconductor device and method of manufacturing the same. The semiconductor device includes a substrate and a through silicon via structure. The through silicon via is disposed in the substrate and includes an insulation layer and a plurality of conductive lines. The conductive lines are separated from each other by the insulation layer and extend from a top surface of the insulation layer to a bottom surface opposite to the top surface.

公开(公告)号：US11024560B2

公开(公告)日：2021-06-01

申请号：US16583290

申请日：2019-09-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor structure including a substrate, a dielectric layer, a conductive via, and a landing pad is provided. The dielectric layer is positioned on the substrate. The conductive via penetrates from a lower surface of the substrate to an upper surface of the dielectric layer. The landing pad is embedded in the conductive via.

公开(公告)号：US10910345B2

公开(公告)日：2021-02-02

申请号：US16401587

申请日：2019-05-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Pei-Jhen Wu ,  Ching-Hung Chang ,  Hsih-Yang Chiu

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/528 ,  H01L23/00 ,  H01L23/498

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first die, a second die, a first redistribution layer, a second redistribution layer, a first interconnect structure, and a second interconnect structure. The second die is stacked on the first die, the first redistribution layer is disposed between a first substrate of the first die and a second ILD layer of the second die, and the second redistribution layer is disposed on a second substrate of the second die. The first interconnect structure connects the first redistribution layer to one of first metal lines of the first die, and the second interconnect structure connects the second redistribution layer to one of the second metal lines in the second ILD layer.

公开(公告)号：US10861711B1

公开(公告)日：2020-12-08

申请号：US16660824

申请日：2019-10-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/48

Abstract: A method of manufacturing a semiconductor structure includes forming a precursor structure including a plurality of conductive pads on a substrate, an etch stop layer between the conductive pads, and an UBM layer on the conductive pads and the etch stop layer. A plurality of mask structures are formed on the UBM layer, and a plurality of openings are formed between thereof. Each of the mask structures is located on one of the conductive pads, and the openings expose a first portion of the UBM layer. A supporting layer is formed in the openings. The mask structures are removed to form a plurality of cavities exposing a second portion of the UBM layer. A conductive material layer is formed in the cavities. The supporting layer is removed. The first portion of the UBM layer is removed to form a plurality of conductive bumps separated from each other.

公开(公告)号：US10811382B1

公开(公告)日：2020-10-20

申请号：US16404830

申请日：2019-05-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Pei-Jhen Wu ,  Hsih-Yang Chiu ,  Chiang-Lin Shih ,  Ching-Hung Chang ,  Yi-Jen Lo

IPC: H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L21/321 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/311

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.