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公开(公告)号:KR100880182B1
公开(公告)日:2009-01-28
申请号:KR1020080058786
申请日:2008-06-23
CPC classification number: H05K1/025 , H01B7/06 , H05K1/0393 , H05K1/118 , H05K2201/0776
Abstract: A flexible printed circuit board for a large capacity signal transmission medium is provided to maintain constant signal transmission quality by maintaining impedance for transmitting the signal with the large capacity. A copper foil signal wiring(310) receives the signal with the large capacity from the TV main board and transmits the signal to a display device. A copper foil ground layer(320) grounds the signal with the large capacity returned from the display device. An insulating layer(330) is adhered between the copper foil signal wiring and the copper foil grounding layer. A first pad(312) and a second pad(314) of the copper foil signal wiring have the width of 80 to 110 um range. The thickness of the first pad and the second pad of the copper foil signal wiring and the copper foil ground layer is 30 to 40 um range. The thickness of the insulating layer has 20 to 30 um range.
Abstract translation: 提供用于大容量信号传输介质的柔性印刷电路板,通过维持用于传输大容量信号的阻抗来保持恒定的信号传输质量。 铜箔信号线(310)从TV主板接收具有大容量的信号,并将该信号发送到显示装置。 铜箔接地层(320)使从显示装置返回的大容量的信号接地。 绝缘层(330)粘附在铜箔信号布线和铜箔接地层之间。 铜箔信号线的第一焊盘(312)和第二焊盘(314)的宽度为80〜110μm。 铜箔信号线和铜箔接地层的第一焊盘和第二焊盘的厚度为30〜40μm。 绝缘层的厚度为20〜30μm。
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公开(公告)号:KR100852003B1
公开(公告)日:2008-08-22
申请号:KR1020070034565
申请日:2007-04-09
Applicant: 한국산업기술대학교산학협력단 , 농업회사법인 에이앤피테크놀로지주식회사
Inventor: 정인호
CPC classification number: H05K1/0215 , H05K1/025 , H05K1/115 , H05K2201/0776
Abstract: A ground structure using via-holes on a PCB(Printed Circuit Board) and a circuit device having the same are provided to enhance accuracy of a design by performing design in consideration of characteristic impedance. A ground structure(20) for a circuit device includes a signal transmission line(210), an upper ground unit(220), a lower ground unit(230), and a plurality of via holes(240). The signal transmission line is formed by patterning an upper metal layer. The upper ground unit is formed to be isolated from both lateral corners of the signal transmission line at a predetermined distance by patterning the upper metal layer. The lower ground unit is formed on a lower metal layer. The via holes connect the upper ground unit and the lower ground unit by passing through an insulating layer(200) and are filled with conductive material inside.
Abstract translation: 提供了在PCB(印刷电路板)上使用通孔的地面结构和具有该通孔的电路装置,以通过考虑特性阻抗进行设计来提高设计的精度。 用于电路装置的接地结构(20)包括信号传输线(210),上接地单元(220),下接地单元(230)和多个通孔(240)。 信号传输线通过图案化上金属层而形成。 上部地面单元通过图案化上部金属层而形成为以预定距离与信号传输线的两个侧角隔离。 下接地单元形成在下金属层上。 通孔通过绝缘层(200)连接上接地单元和下接地单元,内部填有导电材料。
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公开(公告)号:KR1020080037468A
公开(公告)日:2008-04-30
申请号:KR1020060104669
申请日:2006-10-26
Applicant: 삼성전자주식회사
Inventor: 정광현
IPC: H05K1/02
CPC classification number: G09G5/003 , G09G2370/12 , H05K1/025 , H05K1/182 , H05K2201/0776
Abstract: A printed circuit board is provided to reduce an error rate and satisfy an impedance range of a TMDS(Transition Minimized Differential Signaling) transmission line as an HDMI(High Definition Multimedia Interface) standard. A printed circuit board(100) includes a plurality of signal layers(140), a ground layer(120), a power layer(130), and an element. The plurality of signal layers include transmission lines(110). The ground layer and the power layer are interposed between the plurality of signals. The element increases capacitance on the transmission lines. A region of the ground layer on a lower part of the element is removed. The removed region of the ground layer is in proportion to a size of the element. The element includes an ESD(ElectroStatic Discharge) preventing element(160) and is connected to the ground layer through a via(170).
Abstract translation: 提供印刷电路板以降低错误率并满足TMDS(Transition Minimized Differential Signaling)传输线作为HDMI(高清多媒体接口)标准的阻抗范围。 印刷电路板(100)包括多个信号层(140),接地层(120),功率层(130)和元件。 多个信号层包括传输线(110)。 接地层和功率层插在多个信号之间。 该元件增加了传输线上的电容。 去除元件下部的接地层的区域。 接地层的去除区域与元件的尺寸成比例。 元件包括ESD(静电放电)防止元件(160),并且通过通孔(170)连接到接地层。
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公开(公告)号:KR101611815B1
公开(公告)日:2016-04-12
申请号:KR1020147026065
申请日:2013-02-28
Applicant: 가부시키가이샤 니혼 마이크로닉스
CPC classification number: H05K1/0298 , H05K1/0233 , H05K1/0242 , H05K1/025 , H05K1/09 , H05K3/46 , H05K2201/0154 , H05K2201/0338 , H05K2201/0391 , H05K2201/0776 , H05K2201/0792 , H05K2201/083 , Y10T29/49155
Abstract: 본발명은, 특성임피던스의조정이용이하고협피치화에도대응가능한다층배선기판과그 제조방법및 프로브카드를제공하는것을과제로하고, 기판위에복수의배선층이절연층을끼우고적층되어있는다층배선기판에있어서, 상기배선층에형성되는배선이제1층과제2층으로이루어지는 2층구조의배선이고, 상기제1층이제1 도전성재료로구성되고, 상기제2층이상기제1 도전성재료보다도비투자율이큰 제2 도전성재료로구성되어있고, 상기 2층구조로함으로써, 상기 2층구조의배선과동일한두께의배선을상기제1 도전성재료만으로구성한경우보다도, 상기배선의특성임피던스가 50옴에가까운값으로조정되어있는다층배선기판과그 제조방법및 프로브카드를제공함으로써그 과제를해결한다.
Abstract translation: 多层布线基板包括层叠在基板上的布线层,每层之间具有绝缘层。 形成在布线层中的导线由第一层和第二层构成,以形成双层结构。 第一层由第一导电材料制成,第二层由具有10以上且大于第一导电材料的相对导磁率的第二导电材料制成。 电线的特性阻抗被调节到比具有与双层结构的导线相同厚度的导线的接近50欧姆的值,并且仅由第一导电材料制成。
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公开(公告)号:KR1020150005860A
公开(公告)日:2015-01-15
申请号:KR1020140083980
申请日:2014-07-04
Applicant: 주식회사 잉크테크
CPC classification number: H05K1/0274 , G06F3/041 , G06F2203/04103 , H01L51/445 , H05K1/0213 , H05K1/0289 , H05K1/0298 , H05K1/0306 , H05K1/032 , H05K1/034 , H05K1/0346 , H05K1/097 , H05K3/0026 , H05K3/06 , H05K3/067 , H05K3/12 , H05K3/1258 , H05K2201/0776 , Y02E10/549 , Y02P70/521 , H01B5/14 , H01B5/00 , H01B13/00
Abstract: 본 발명은 전도성 투명기판 제조방법에 관한 것이며, 본 발명의 전도성 투명기판 제조방법은 기판 상에 상호 이격되도록 배열되는 복수개의 주전극을 형성하는 주전극 형성단계; 복수개의 주전극이 서로 전기적으로 단절되는 복수개의 그룹전극으로 그룹화되도록 둘 이상의 주전극을 전기적으로 연결하는 연결전극을 형성하는 연결전극 형성단계;를 포함하는 것을 특징으로 한다.
따라서, 본 발명에 의하면, 투과성이 우수한 전도성 투명기판을 높은 수율의 공정을 통하여 제작할 수 있는 전도성 투명기판 제조방법 및 전도성 투명기판이 제공된다.Abstract translation: 本发明涉及导电性透明基板的制造方法。 根据本发明的导电透明基板的制造方法包括:主电极形成步骤,形成分开设置在基板上的多个主电极; 以及连接电极形成步骤,形成连接电极以电连接两个或更多个主电极,以将主电极分组成多个电断开的组电极。 因此,根据本发明,提供了能够通过高收率工艺制造具有高透射率的导电透明基板的导电透明基板和导电透明基板的制造方法。
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公开(公告)号:KR1020100001453A
公开(公告)日:2010-01-06
申请号:KR1020080061353
申请日:2008-06-27
Applicant: 주식회사 도담시스템스
Inventor: 오정상
IPC: H05K1/02
CPC classification number: H05K1/025 , H05K2201/0776
Abstract: PURPOSE: A printed circuit board is provided to prevent an error in a data reading and writing operation by preventing the delay of a signal regardless of the sudden temperature change. CONSTITUTION: A printed circuit board includes an address line(10), a data line(20), and a clock line(30). A pattern length of the address line is same as the pattern length of the data line. The pattern length of the clock line is 2 to 5 mm longer than the pattern length of the data line. The pattern length of the address line and the data line is 15 to 60 mm. The pattern thickness of the address line, the data line, and the clock line is 0.2 to 0.3 mm.
Abstract translation: 目的:提供印刷电路板,以防止数据读写操作中的错误,防止信号的延迟,而不管突然的温度变化如何。 构成:印刷电路板包括地址线(10),数据线(20)和时钟线(30)。 地址线的图案长度与数据线的图案长度相同。 时钟线的图案长度比数据线的图案长度长2-5mm。 地址线和数据线的图案长度为15〜60mm。 地址线,数据线和时钟线的图案厚度为0.2〜0.3mm。
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公开(公告)号:KR1020090072154A
公开(公告)日:2009-07-02
申请号:KR1020070140178
申请日:2007-12-28
Applicant: 엘지전자 주식회사
IPC: H05K3/46
CPC classification number: H05K3/4644 , H05K1/025 , H05K3/0011 , H05K2201/0776
Abstract: A multilayer PCB is provided to reduce thickness and manufacturing cost by forming a reference layer in an inner region corresponding to a high speed operation circuit mounting region. A multilayer PCB includes a plurality of signal layers(202,204,206,208), a plurality of insulation layers(210), and reference layers(214,216). A pattern for electrically connecting a power pattern, a ground pattern, and electronic parts is formed on a plurality of signal layers. A plurality of insulation layers electrically insulates a plurality of signal layers. The reference layers are formed in an inner region corresponding to a high speed operation circuit mounting region in order to match impedance of a high speed operation circuit(212). The reference layers are electrically connected to the power pattern or the ground pattern through a via hole. The high speed operation circuit includes one or more among a DDR(Dual Data Rate) memory, a USB(Universal Serial Bus), and a HDMI(High Density Multimedia Interface).
Abstract translation: 提供多层PCB,以通过在对应于高速运算电路安装区域的内部区域中形成参考层来减小厚度和制造成本。 多层PCB包括多个信号层(202,204,206,208),多个绝缘层(210)和参考层(214,216)。 在多个信号层上形成用于电连接功率图案,接地图案和电子部件的图案。 多个绝缘层使多个信号层电绝缘。 参考层形成在对应于高速运算电路安装区域的内部区域中,以匹配高速运算电路(212)的阻抗。 参考层通过通孔电连接到功率图案或接地图案。 高速运算电路包括DDR(双数据速率)存储器,USB(通用串行总线)和HDMI(高密度多媒体接口)中的一个或多个。
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公开(公告)号:KR1020090042668A
公开(公告)日:2009-04-30
申请号:KR1020070108541
申请日:2007-10-26
Applicant: 삼성전기주식회사
IPC: H05K1/02
CPC classification number: H05K1/0224 , H05K1/025 , H05K2201/0776
Abstract: A printed circuit board and a manufacturing method thereof are provided to reduce the capacitance by applying a low dielectric constant material between adjacent patterns. A printed circuit board includes an insulating layer, a metal layer(10a,10b) and a pattern(31,32). The metal layer is laminated on both sides of the insulating layer. The insulating layer includes a pattern insulating layer(22), a first insulation layer(21) and a second insulation layer(23). The pattern is reclaimed in the pattern insulating layer. The first insulation layer is laminated on one side of the pattern insulating layer. The second insulating layer is laminated on other side of the pattern insulating layer. The pattern insulating layer is made of the material with the dielectric constant lower than the dielectric constant of the first insulating layer. The pattern insulating layer is made of the material in which the dielectric constant is lower than the first insulation layer. The pattern insulating layer includes polyphenylenether or Teflon.
Abstract translation: 提供印刷电路板及其制造方法,以通过在相邻图案之间施加低介电常数材料来减小电容。 印刷电路板包括绝缘层,金属层(10a,10b)和图案(31,32)。 金属层层压在绝缘层的两侧。 绝缘层包括图案绝缘层(22),第一绝缘层(21)和第二绝缘层(23)。 图案在图案绝缘层中回收。 第一绝缘层层叠在图案绝缘层的一侧。 第二绝缘层层叠在图案绝缘层的另一侧。 图案绝缘层由介电常数低于第一绝缘层的介电常数的材料制成。 图案绝缘层由介电常数低于第一绝缘层的材料制成。 图案绝缘层包括聚苯乙烯或聚四氟乙烯。
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公开(公告)号:KR101717983B1
公开(公告)日:2017-03-21
申请号:KR1020140083980
申请日:2014-07-04
Applicant: 주식회사 잉크테크
CPC classification number: H05K1/0274 , G06F3/041 , G06F2203/04103 , H01L51/445 , H05K1/0213 , H05K1/0289 , H05K1/0298 , H05K1/0306 , H05K1/032 , H05K1/034 , H05K1/0346 , H05K1/097 , H05K3/0026 , H05K3/06 , H05K3/067 , H05K3/12 , H05K3/1258 , H05K2201/0776 , Y02E10/549 , Y02P70/521
Abstract: 본발명은전도성투명기판제조방법에관한것이며, 본발명의전도성투명기판제조방법은기판상에상호이격되도록배열되는복수개의주전극을형성하는주전극형성단계; 복수개의주전극이서로전기적으로단절되는복수개의그룹전극으로그룹화되도록둘 이상의주전극을전기적으로연결하는연결전극을형성하는연결전극형성단계;를포함하는것을특징으로한다. 따라서, 본발명에의하면, 투과성이우수한전도성투명기판을높은수율의공정을통하여제작할수 있는전도성투명기판제조방법및 전도성투명기판이제공된다.
Abstract translation: 本发明涉及一种用于制备导电透明基板,本发明的透明导电性基板的制造方法是在形成多个被布置成彼此在基底上间隔开主电极的步骤的主电极; 并且形成电连接两个或更多个主电极的连接电极,使得多个主电极分组为彼此电断开的多个组电极。 因此,根据本发明,提供了一种导电透明基板制造方法和导电透明基板,其可以通过具有优异透明度的导电透明基板的高产率工艺来制造。
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公开(公告)号:KR1020160150108A
公开(公告)日:2016-12-28
申请号:KR1020167035463
申请日:2013-05-31
Applicant: 닛토덴코 가부시키가이샤
CPC classification number: H05K1/0213 , C23C14/086 , G06F3/041 , H05K1/0274 , H05K1/032 , H05K1/0326 , H05K1/09 , H05K3/16 , H05K3/22 , H05K2201/0145 , H05K2201/0158 , H05K2201/0326 , H05K2201/0776 , H05K2203/1194 , Y10T428/31507 , Y10T428/31786 , Y10T428/31938 , H01B5/14 , B32B9/00 , C23C14/08 , C23C14/34
Abstract: 투과율이높고, 또한비저항이작은투명도전성필름을제공한다. 본실시형태에관련된투명도전성필름 (1) 은, 필름기재 (2) 와, 그필름기재상에형성된인듐주석산화물의다결정층 (3) 을구비하고있다. 이다결정층 (3) 은, 두께가 10 ㎚∼ 30 ㎚이고, 결정입경의평균값이 180 ㎚∼ 270 ㎚이고, 또한캐리어밀도가 6 × 10개/㎤를 초과하고 9 × 10개/㎤이하이다.
Abstract translation: 透明导电膜包括在基底上形成的膜基底和氧化铟锡的多晶层。 多晶层的厚度为10nm至30nm,增益尺寸的平均值为180nm至270nm,载流子密度大于6×1020 / cm3,小于或等于9×1020 / cm3。
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