公开(公告)号：WO2007138063A1

公开(公告)日：2007-12-06

申请号：PCT/EP2007/055211

申请日：2007-05-29

Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC) ,  UMICORE ,  LEYS, Frederik ,  BONZOM, Renaud ,  CAYMAX, Matty ,  LOO, Roger

Inventor： LEYS, Frederik ,  BONZOM, Renaud ,  CAYMAX, Matty ,  LOO, Roger

IPC: H01L21/20 ,  H01L21/205

CPC classification number: C30B29/08 ,  C30B25/20 ,  C30B29/04 ,  C30B29/06 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02634

Abstract: The invention relates to a method for improving the surface roughness of a semiconductor substrate. A method is provided for reducing the roughness of a semiconductor substrate surface comprising the steps of: providing a semiconductor substrate, the surface of which comprises a group IV mono-crystalline semiconductor material, and depositing, on said group IV mono-crystalline semiconductor material, a layer of (substantially) the same group IV mono-crystalline semiconductor material, by a deposition technique using nitrogen and/or at least one noble gas as carrier gas.

Abstract translation: 本发明涉及一种改善半导体衬底的表面粗糙度的方法。 提供了一种降低半导体衬底表面粗糙度的方法，包括以下步骤：提供半导体衬底，其表面包括IV族单晶半导体材料，并在所述IV族单晶半导体材料上沉积， 通过使用氮气和/或至少一种惰性气体作为载气的沉积技术形成（基本上）相同的IV族单晶半导体材料层。

公开(公告)号：WO2012130933A1

公开(公告)日：2012-10-04

申请号：PCT/EP2012055620

申请日：2012-03-29

Applicant: IMEC ,  UNIV LEUVEN KATH ,  VINCENT BENJAMIN ,  GENCARELLI FEDERICA ,  LOO ROGER ,  CAYMAX MATTY

Inventor： VINCENT BENJAMIN ,  GENCARELLI FEDERICA ,  LOO ROGER ,  CAYMAX MATTY

IPC: H01L21/02 ,  H01L21/205

CPC classification number: H01L21/02532 ,  H01L21/02535 ,  H01L21/0262

Abstract: A method is provided for depositing a monocrystalline Sn-containing semiconductor material on a substrate, comprising providing a semiconductor material precursor, a Sn precursor and a carrier gas in a chemical vapor deposition (CVD) reactor, and epitaxially growing the Sn- containing semiconductor material on the substrate, wherein the Sn precursor comprises tin tetrachloride (SnC14). SnC14 is used as Sn-precursor for chemical vapor deposition of Sn comprising semiconductor materials.

Abstract translation: 提供了一种用于在衬底上沉积单晶含Sn半导体材料的方法，包括在化学气相沉积（CVD）反应器中提供半导体材料前体，Sn前体和载气，并外延生长含Sn半导体材料 其中Sn前体包括四氯化锡（SnC14）。 SnC14用作用于Sn的半导体材料的化学气相沉积的Sn前体。

公开(公告)号：WO0174708A3

公开(公告)日：2002-03-21

申请号：PCT/IB0100765

申请日：2001-04-05

Applicant: IMEC INTER UNI MICRO ELECTR ,  SEDKY SHERIF ,  WITVROUW ANN ,  BAERT KRIS ,  CAYMAX MATTY ,  RUSU CRISTINA

Inventor： SEDKY SHERIF ,  WITVROUW ANN ,  BAERT KRIS ,  CAYMAX MATTY ,  RUSU CRISTINA

IPC: B81C1/00 ,  C23C16/22 ,  H01L21/205 ,  H01L31/0368 ,  H01L31/18 ,  B81B3/00

CPC classification number: C23C16/22 ,  B81C1/00365 ,  B81C2201/0164 ,  B81C2201/017 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L31/03682 ,  H01L31/1812 ,  Y02E10/546

Abstract: Method and apparatus of to obtain as-deposited polycrystalline and low-stress SiGe layers. These layers are used in Micro Electro-Mechanical Systems (MEMS) devices or micromachined structures. Different parameters are analysed which effect the stress in a polycrystalline layer. The parameters include, without limitation: deposition temperature; concentration of semiconductors (e.g., the concentration of Silicon and Germanium in a SixGe1-x layer, with x being the concentration parameter); concentration of dopants (e.g., the concentration of Boron or Phosphorous); amount of pressure; and use of plasma. Depending on the particular environment in which the polycrystalline SiGe is grown, different values of parameters are used.

Abstract translation: 获得沉积的多晶和低应力SiGe层的方法和设备。 这些层用于微机电系统（MEMS）装置或微加工结构。 分析影响多晶层中的应力的不同参数。 参数包括但不限于：沉积温度; 半导体的浓度（例如，SixGe1-x层中的硅和锗的浓度，x是浓度参数）; 掺杂剂的浓度（例如硼或磷的浓度）; 压力量; 并使用等离子体。 取决于多晶SiGe生长的特定环境，使用不同的参数值。

公开(公告)号：WO2010003928A2

公开(公告)日：2010-01-14

申请号：PCT/EP2009/058529

申请日：2009-07-06

Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) ,  LOO, Roger ,  LEYS, Frederik ,  CAYMAX, Matty

Inventor： LOO, Roger ,  LEYS, Frederik ,  CAYMAX, Matty

IPC: H01L21/225 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/2254 ,  H01L21/2256 ,  H01L29/1054 ,  H01L29/66803 ,  H01L29/7842

Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.

Abstract translation: 一种用于将物质引入应变半导体层的方法，包括：提供包括第一区域和第二区域的衬底，所述第一区域包括暴露的应变半导体层，将所述衬底装载到反应室中，然后形成共形第一物质， 至少在暴露的应变半导体层上，然后进行热处理，由此使第一种类的至少一部分从第一种类层扩散到应变半导体层中，并且至少部分地激活 在应变半导体层中扩散的第一类物质。

公开(公告)号：WO2004053997A1

公开(公告)日：2004-06-24

申请号：PCT/BE2003/000213

申请日：2003-12-09

Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC) ,  ASM AMERICA INC. ,  CHEN, Jerry ,  WILMAN, Tsai ,  CAYMAX, Matty ,  MAES, Jan-Willem

Inventor： CHEN, Jerry ,  WILMAN, Tsai ,  CAYMAX, Matty ,  MAES, Jan-Willem

IPC: H01L29/43

CPC classification number: H01L21/28194 ,  C23C16/0218 ,  C23C16/308 ,  C23C16/345 ,  C23C16/405 ,  C23C16/45525 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31645 ,  H01L21/318 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting said semiconductor substrate with said high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor phase reactant in a plasma-enhanced chemical vapor deposition process (PECVD) or a plasma-enhanced atomic layer chemical vapor deposition (PE ALCVD) process. Furthermore, the present invention provides a dielectric stack in an integrated circuit comprising (i) a high-k dielectric layer comprising at least a high-k material, (ii) a dielectric layer comprising at least silicon and nitrogen; (iii) an intermediate layer disposed between said high-k dielectric layer and said dielectric layer, said intermediate layer comprising said high-k material, silicon and nitrogen.

Abstract translation: 本发明提供了一种用于在集成电路中制造电介质叠层的方法，包括以下步骤：（i）在半导体衬底上形成高k电介质层，（ii）使所述半导体衬底与所述高k电介质层对 包含气相反应物的氮和包含气相反应物的硅在等离子体增强化学气相沉积工艺（PECVD）或等离子体增强原子层化学气相沉积（PE ALCVD）工艺中。 此外，本发明提供了一种集成电路中的电介质堆叠，包括（i）至少包含高k材料的高k电介质层，（ii）至少包含硅和氮的电介质层; （iii）设置在所述高k电介质层和所述电介质层之间的中间层，所述中间层包含所述高k材料，硅和氮。

公开(公告)号：WO2012130933A9

公开(公告)日：2012-10-04

申请号：PCT/EP2012/055620

申请日：2012-03-29

Applicant: IMEC ,  KATHOLIEKE UNIVERSITEIT LEUVEN ,  VINCENT, Benjamin ,  GENCARELLI, Federica ,  LOO, Roger ,  CAYMAX, Matty

Inventor： VINCENT, Benjamin ,  GENCARELLI, Federica ,  LOO, Roger ,  CAYMAX, Matty

IPC: H01L21/02 ,  H01L21/205

Abstract: A method is provided for depositing a monocrystalline Sn-containing semiconductor material on a substrate, comprising providing a semiconductor material precursor, a Sn precursor and a carrier gas in a chemical vapor deposition (CVD) reactor, and epitaxially growing the Sn- containing semiconductor material on the substrate, wherein the Sn precursor comprises tin tetrachloride (SnC14). SnC1 4 is used as Sn-precursor for chemical vapor deposition of Sn comprising semiconductor materials.

公开(公告)号：WO2010003928A3

公开(公告)日：2010-05-06

申请号：PCT/EP2009058529

申请日：2009-07-06

Applicant: IMEC INTER UNI MICRO ELECTR ,  LOO ROGER ,  LEYS FREDERIK ,  CAYMAX MATTY

Inventor： LOO ROGER ,  LEYS FREDERIK ,  CAYMAX MATTY

IPC: H01L21/225 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/2254 ,  H01L21/2256 ,  H01L29/1054 ,  H01L29/66803 ,  H01L29/7842

Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.

Abstract translation: 一种用于将物质引入应变半导体层的方法，包括：提供包括包含暴露的应变半导体层的第一区域的衬底，将衬底装载在反应室中，然后通过气相沉积（VPD）形成保形的第一种容纳层， 至少在暴露的应变半导体层上，然后进行热处理，从而使至少部分第一种类从第一种含有层扩散到应变半导体层中，并激活至少部分扩散的第一种类在应变半导体层 半导体层。

公开(公告)号：WO2004064130A1

公开(公告)日：2004-07-29

申请号：PCT/BE2004/000009

申请日：2004-01-14

Applicant: UNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC) ,  KRONINKLIJKE PHILIPS ELECTRONICS ,  DELHOUGNE, Romain ,  LOO, Roger ,  MEUNIER-BEILLARD, Philippe ,  CAYMAX, Matty

Inventor： DELHOUGNE, Romain ,  LOO, Roger ,  MEUNIER-BEILLARD, Philippe ,  CAYMAX, Matty

IPC: H01L21/20

CPC classification number: H01L29/107 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02667 ,  H01L29/1054

Abstract: The invention relates to a semiconductor device comprising a semiconductor substrate and having on its top at least a Thin Strain Relaxed Buffer, consisting essentially of a stack of three layers, characterized in that the Thin Strain Relaxed Buffer is not an active part of the semiconductor device and in that said three layers defining the Thin Strain Relaxed Buffer have an essentially constant Ge concentration, said three layers being: - a first epitaxial layer of Si 1-x Ge x , x being the Ge concentration; - a second epitaxial layer of Si 1-x Ge x : C on said first epitaxial layer, the amount of C being at least 0.3 %; - a third epitaxial layer of Si 1-x Ge x on said second layer.

Abstract translation: 本发明涉及一种半导体器件，其包括半导体衬底，并且在其顶部至少具有由三层叠层构成的薄应变松弛缓冲器，其特征在于薄应变弛豫缓冲器不是半导体器件的有源部分 并且所述限定薄应变松弛缓冲液的三个层具有基本上恒定的Ge浓度，所述三个层是： - Si1-xGex的第一外延层，x是Ge浓度; - 在所述第一外延层上的Si1-xGex：C的第二外延层，C的量为至少0.3％; - 所述第二层上的Si1-xGex的第三外延层。