IN SYSTEM ANALYSIS AND COMPENSATION FOR A DIGITAL PWM CONTROLLER
    1.
    发明申请
    IN SYSTEM ANALYSIS AND COMPENSATION FOR A DIGITAL PWM CONTROLLER 审中-公开
    数字PWM控制器的系统分析与补偿

    公开(公告)号:WO2007041554A3

    公开(公告)日:2007-12-13

    申请号:PCT/US2006038571

    申请日:2006-09-29

    Abstract: A system for analyzing the operation of a switching power converter includes a digital controller for receiving an analog signal representing the output DC voltage of the power converter for comparison to a desired output voltage level and generating switching control signals to control the operation of the power supply to regulate the output DC voltage to said output voltage level. At least one portion of a control loop within the digital controller may he switched into the control loop in a first mode of operation and out of the control loop in a second mode of operation. A microcontroller emulates the operation of the at least one portion of the control loop during the second mode of operation.

    Abstract translation: 一种用于分析开关功率变换器的操作的系统包括:数字控制器,用于接收表示功率变换器的输出DC电压的模拟信号,用于与期望的输出电压电平进行比较,并产生开关控制信号以控制电源的操作 以将输出DC电压调节到所述输出电压电平。 数字控制器内的控制回路的至少一部分可以在第一操作模式下切换到控制回路中并且在第二操作模式下切换到控制回路外。 微控制器在第二操作模式期间模拟控制回路的至少一部分的操作。

    IN SYSTEM ANALYSIS AND COMPENSATION FOR A DIGITAL PWM CONTROLLER
    2.
    发明申请
    IN SYSTEM ANALYSIS AND COMPENSATION FOR A DIGITAL PWM CONTROLLER 审中-公开
    用于数字PWM控制器的系统分析和补偿

    公开(公告)号:WO2007041554A2

    公开(公告)日:2007-04-12

    申请号:PCT/US2006/038571

    申请日:2006-09-29

    Abstract: A system for analyzing the operation of a switching power converter includes a digital controller for receiving an analog signal representing the output DC voltage of the power converter for comparison to a desired output voltage level and generating switching control signals to control the operation of the power supply to regulate the output DC voltage to said output voltage level. At least one portion of a control loop within the digital controller may he switched into the control loop in a first mode of operation and out of the control loop in a second mode of operation. A microcontroller emulates the operation of the at least one portion of the control loop during the second mode of operation.

    Abstract translation: 用于分析开关功率转换器的操作的系统包括数字控制器,用于接收表示功率转换器的输出直流电压的模拟信号,以便与期望的输出电压电平进行比较,并产生开关控制信号以控制电源的操作 以将输出DC电压调节到所述输出电压电平。 数字控制器内的控制回路的至少一部分可以在第二操作模式中以第一操作模式切换到控制回路中,并且在第二操作模式中切换到控制回路中。 微控制器在第二操作模式期间模拟控制回路的至少一部分的操作。

    CONFIGURABLE PING-PONG BUFFERS FOR USB BUFFER DESCRIPTION TABLES

    公开(公告)号:WO2005119468A3

    公开(公告)日:2005-12-15

    申请号:PCT/US2005/018649

    申请日:2005-05-26

    Abstract: A digital device having selectable modes for USB communications buffer management in a USB interface of the digital device. These modes may comprise (1) no ping-pong buffer support, (2) ping-pong buffer support for some endpoints, e.g., support for OUT endpoint 0 only, and (3) ping-pong buffer support for all endpoints. In the no ping-pong buffer support mode, no hardware is required for automatic ping-pong buffer management. In the ping-pong buffer support for OUT endpoint 0 only mode, endpoint 0 setup transfers may be serviced without delay while only requiring a minimal number of memory locations for the remainder of the buffer descriptors. In the ping-pong buffer support for all endpoints mode, automatic ping-pong buffer management may be provided for all endpoints. This mode assures that all endpoint transfers may be serviced substantially without delay.

    CONFIGURABLE PING-PONG BUFFERS FOR USB BUFFER DESCRIPTION TABLES
    4.
    发明申请
    CONFIGURABLE PING-PONG BUFFERS FOR USB BUFFER DESCRIPTION TABLES 审中-公开
    USB缓冲区描述表的可配置PING-PONG BUFFERS

    公开(公告)号:WO2005119468A2

    公开(公告)日:2005-12-15

    申请号:PCT/US2005018649

    申请日:2005-05-26

    CPC classification number: G06F13/38

    Abstract: A digital device having selectable modes for USB communications buffer management in a USB interface of the digital device. These modes may comprise (1) no ping-pong buffer support, (2) ping-pong buffer support for some endpoints, e.g., support for OUT endpoint 0 only, and (3) ping-pong buffer support for all endpoints. In the no ping­pong buffer support mode, no hardware is required for automatic ping-pong buffer management. The Buffer Descriptor Tables may comprise a maximum of 128 memory locations, e.g., 16 IN endpoints and 16 OUT endpoints, each with at least one buffer descriptor, and each comprising four (4) memory locations. In the ping-pong buffer support for OUT endpoint 0 only mode, the buffer descriptor Tables may comprise a maximum of 132 memory locations, e.g., 16 OUT endpoints with an EVEN and an ODD endpoint 0, 16 IN endpoints, each with at least one descriptor, e.g., memory locations. This mode assures that endpoint 0 setup transfers may be serviced without delay while only requiring a minimal number of memory locations for the remainder of the buffer descriptors. In the ping-pong buffer support for all endpoints mode, automatic ping-pong buffer management may be provided for all endpoints. The Buffer Descriptor Tables may comprise a maximum of 256 memory locations, e.g., 16 IN endpoints and 16 OUT endpoints, an EVEN and ODD set for each, each with one descriptor, e.g., four (4) memory locations. This mode assures that all endpoint transfers may be serviced substantially without delay.

    Abstract translation: 一种数字设备,其具有用于在数字设备的USB接口中进行USB通信缓冲器管理的可选模式。 这些模式可以包括(1)无乒乓缓冲器支持,(2)对某些端点的乒乓缓冲器支持,例如仅支持OUT端点0,以及(3)对所有端点的乒乓缓冲器支持。 在无乒乓缓冲支持模式下,无需硬件自动乒乓缓冲区管理。 缓冲器描述符表可以包括最多128个存储器位置,例如16个IN端点和16个OUT端点,每个具有至少一个缓冲器描述符,并且每个包括四(4)个存储单元。 在乒乓缓冲区支持OUT端点0唯一模式下,缓冲区描述符表可以包含最多132个存储器位置,例如16个OUT端点,其中EVEN和ODD端点为0,16 IN端点,每个端点至少有一个 描述符,例如内存位置。 该模式确保端点0建立传输可以无延迟地被服务,而仅需要缓冲器描述符的其余部分的最小数量的存储器位置。 在所有端点模式的乒乓缓冲区支持中,可以为所有端点提供自动乒乓缓冲区管理。 缓冲器描述符表可以包括最多256个存储器位置,例如16个IN端点和16个OUT端点,为每个存储单元设置一个EVEN和ODD,每个具有一个描述符,例如四(4)个存储器位置。 该模式确保所有端点传输可以在没有延迟的情况下得到实质的维护。

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