公开(公告)号：WO2008127984A1

公开(公告)日：2008-10-23

申请号：PCT/US2008/059911

申请日：2008-04-10

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  WOJEWODA, Igor ,  MARNEWECK, Kobus

Inventor： WOJEWODA, Igor ,  MARNEWECK, Kobus

IPC: G06F11/10

CPC classification number: G06F11/1052

Abstract: Memory space of a digital device may be configured for both instructions/data (op- code) and ECC or parity when required, otherwise the entire memory space may be configured for just the program instructions/data. A standard word width memory may be configured for ECC or non-ECC functionality, or parity or non-parity functionality, based upon a desired application. The last portion of the memory may be allocated for ECC or parity data rather then application code when an ECC or parity implementation is required. When an ECC or parity implementation is not required, the entire memory may be used for the application code. This allows a digital device and memory to be used in applications having different robustness (e.g., application code integrity) requirements without have to fabricate different digital devices.

Abstract translation: 数字设备的存储空间可以在需要时配置为指令/数据（操作码）和ECC或奇偶校验，否则整个存储器空间可以仅被配置为程序指令/数据。 基于期望的应用，标准字宽存储器可以被配置用于ECC或非ECC功能，或奇偶校验或非奇偶校验功能。 存储器的最后部分可以被分配用于ECC或奇偶校验数据，而不是需要ECC或奇偶校验实现时的应用代码。 当不需要ECC或奇偶校验实现时，整个存储器可以用于应用代码。 这允许将数字设备和存储器用于具有不同鲁棒性（例如，应用代码完整性）要求的应用中，而不必制造不同的数字设备。

公开(公告)号：WO2008073883A2

公开(公告)日：2008-06-19

申请号：PCT/US2007/086963

申请日：2007-12-10

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  SIMMONS, Michael ,  WOJEWODA, Igor

Inventor： SIMMONS, Michael ,  WOJEWODA, Igor

IPC: H03K19/00

CPC classification number: G06F1/3203 ,  G06F1/24

Abstract: A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a "low power state wake-up and restore" signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.

Abstract translation: 半导体集成电路器件在从低功率模式退出时，唤醒并重新初始化逻辑电路，以便恢复内部寄存器的先前逻辑状态，而不会干扰当前存在的输入输出（I / O）配置控制和数据状态 输入低功耗模式。 因此，在低功率模式下，不能分配连接到半导体集成电路器件的其它器件的操作。 一旦半导体集成电路器件的所有内部逻辑和寄存器被重新初始化，就可能发出“低功率状态唤醒和恢复”信号。 该信号表示在集成电路器件进入低功率模式时存储在I / O保持器单元中的I / O配置控制和数据状态已被恢复，并且可以将控制返回到逻辑电路和/或内部 半导体集成电路器件的寄存器。

公开(公告)号：WO2008014370A3

公开(公告)日：2008-04-17

申请号：PCT/US2007074405

申请日：2007-07-26

Applicant: MICROCHIP TECH INC ,  WOJEWODA IGOR ,  LOURENS RUAN

Inventor： WOJEWODA IGOR ,  LOURENS RUAN

IPC: G06F13/40 ,  H01L23/48

CPC classification number: G06F13/4072 ,  H01L2224/05554

Abstract: A microcontroller may have at least a first and second output port coupled with external first and second pins, respectively, a programmable switching arrangement operable in a first mode to provide for a first and second output signal at the first and second pins, respectively, and in a second mode to provide for a first output signal at the first pin and an inverted first output signal at the second pin.

Abstract translation: 微控制器可以具有至少第一和第二输出端口，分别与外部第一和第二引脚耦合，可编程开关装置可在第一模式下操作以分别在第一和第二引脚处提供第一和第二输出信号，以及 在第二模式中提供第一引脚处的第一输出信号和第二引脚处的反相第一输出信号。

公开(公告)号：WO2008130909A1

公开(公告)日：2008-10-30

申请号：PCT/US2008/060314

申请日：2008-04-15

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  WOJEWODA, Igor ,  KAVAIYA, Gaurang ,  PHOENIX, Tim

Inventor： WOJEWODA, Igor ,  KAVAIYA, Gaurang ,  PHOENIX, Tim

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1028 ,  H03M1/1225

Abstract: A mixed signal device having an analog-to-digital converter (ADC) with offset and gain calibration using internal voltage references whereby the digital processor calibrates out offset and gain errors in the analog-to-digital converter by adjusting the analog input amplifier gain and offset or with software compensating the digital representations of the voltages measured. Two different known voltage values are used in determining the offset and gain adjustments needed to calibrate the ADC against the two know voltage values. The mixed signal device may further comprise a Bandgap voltage reference having an accurate known voltage value. Wherein the Bandgap voltage reference may be used for further offset and gain calibration of the ADC to produce substantially absolute voltage values.

Abstract translation: 一种混合信号装置，其具有使用内部电压基准的具有偏移和增益校准的模数转换器（ADC），由此数字处理器通过调整模拟输入放大器增益来校准模拟 - 数字转换器中的失调和增益误差， 补偿或补偿测量电压的数字表示。 使用两种不同的已知电压值来确定根据两个已知电压值校准ADC所需的偏移和增益调整。 混合信号装置还可以包括具有精确的已知电压值的带隙电压基准。 其中带隙参考电压可用于ADC的进一步偏移和增益校准，以产生基本上绝对的电压值。

公开(公告)号：WO2007143494A3

公开(公告)日：2008-03-13

申请号：PCT/US2007070066

申请日：2007-05-31

Applicant: MICROCHIP TECH INC ,  WOJEWODA IGOR ,  BOLES BRIAN ,  BRADLEY STEVE ,  KAVAIYA GAURANG

Inventor： WOJEWODA IGOR ,  BOLES BRIAN ,  BRADLEY STEVE ,  KAVAIYA GAURANG

IPC: H03K19/0175

CPC classification number: H03K19/17764 ,  H03K19/1732 ,  H03K19/17744

Abstract: Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input- output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.

Abstract translation: 通过使用一组配置寄存器，集成电路设备的外围功能可以被集合并且动态地映射到集成电路设备的可用的外部输入 - 输出连接。 为了提供系统的鲁棒性，配置寄存器可以实现各种级别的写保护，纠错和监视电路。 一个或多个外围输出功能可以映射到一个或多个外部输出连接。 在同一输出连接上，同一输出功能可能同时处于活动状态。 输出和输入可以被映射到相同的外部输入 - 输出连接，具有或不具有可控制的输出以放置到非活动状态，例如高阻抗或开路集电极。 当输入需要通过外部输入 - 输出连接接收外部数据时，输出可能被置于非活动状态。

公开(公告)号：WO2005119468A2

公开(公告)日：2005-12-15

申请号：PCT/US2005018649

申请日：2005-05-26

Applicant: MICROCHIP TECH INC ,  WOJEWODA IGOR ,  FOSLER ROSS ,  ROJVANIT RAWIN

Inventor： WOJEWODA IGOR ,  FOSLER ROSS ,  ROJVANIT RAWIN

IPC: G06F13/38

CPC classification number: G06F13/38

Abstract: A digital device having selectable modes for USB communications buffer management in a USB interface of the digital device. These modes may comprise (1) no ping-pong buffer support, (2) ping-pong buffer support for some endpoints, e.g., support for OUT endpoint 0 only, and (3) ping-pong buffer support for all endpoints. In the no ping­pong buffer support mode, no hardware is required for automatic ping-pong buffer management. The Buffer Descriptor Tables may comprise a maximum of 128 memory locations, e.g., 16 IN endpoints and 16 OUT endpoints, each with at least one buffer descriptor, and each comprising four (4) memory locations. In the ping-pong buffer support for OUT endpoint 0 only mode, the buffer descriptor Tables may comprise a maximum of 132 memory locations, e.g., 16 OUT endpoints with an EVEN and an ODD endpoint 0, 16 IN endpoints, each with at least one descriptor, e.g., memory locations. This mode assures that endpoint 0 setup transfers may be serviced without delay while only requiring a minimal number of memory locations for the remainder of the buffer descriptors. In the ping-pong buffer support for all endpoints mode, automatic ping-pong buffer management may be provided for all endpoints. The Buffer Descriptor Tables may comprise a maximum of 256 memory locations, e.g., 16 IN endpoints and 16 OUT endpoints, an EVEN and ODD set for each, each with one descriptor, e.g., four (4) memory locations. This mode assures that all endpoint transfers may be serviced substantially without delay.

Abstract translation: 一种数字设备，其具有用于在数字设备的USB接口中进行USB通信缓冲器管理的可选模式。 这些模式可以包括（1）无乒乓缓冲器支持，（2）对某些端点的乒乓缓冲器支持，例如仅支持OUT端点0，以及（3）对所有端点的乒乓缓冲器支持。 在无乒乓缓冲支持模式下，无需硬件自动乒乓缓冲区管理。 缓冲器描述符表可以包括最多128个存储器位置，例如16个IN端点和16个OUT端点，每个具有至少一个缓冲器描述符，并且每个包括四（4）个存储单元。 在乒乓缓冲区支持OUT端点0唯一模式下，缓冲区描述符表可以包含最多132个存储器位置，例如16个OUT端点，其中EVEN和ODD端点为0,16 IN端点，每个端点至少有一个 描述符，例如内存位置。 该模式确保端点0建立传输可以无延迟地被服务，而仅需要缓冲器描述符的其余部分的最小数量的存储器位置。 在所有端点模式的乒乓缓冲区支持中，可以为所有端点提供自动乒乓缓冲区管理。 缓冲器描述符表可以包括最多256个存储器位置，例如16个IN端点和16个OUT端点，为每个存储单元设置一个EVEN和ODD，每个具有一个描述符，例如四（4）个存储器位置。 该模式确保所有端点传输可以在没有延迟的情况下得到实质的维护。

公开(公告)号：WO2005043385A1

公开(公告)日：2005-05-12

申请号：PCT/US2004/034730

申请日：2004-10-20

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  WOJEWODA, Igor ,  TRIECE, Joseph, W.

Inventor： WOJEWODA, Igor ,  TRIECE, Joseph, W.

IPC: G06F9/318

CPC classification number: G06F9/30145 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3822

Abstract: A method, system and apparatus are provided for alternating instruction sets in central processing units. A microcontroller is provided with a configuration mechanism, such as a fuse that, depending upon the setting, determines which of multiple instruction sets (or multiple parts of a single instruction set) can be processed by the central processing unit. By changing the fuse setting the characteristics of the central processing unit, and thus the microcontroller as a whole, can be changed.

Abstract translation: 提供了一种用于在中央处理单元中交替指令集的方法，系统和装置。 微控制器具有配置机构，例如根据该设置确定中央处理单元可以处理多个指令集（或单个指令集的多个部分）哪一个）的保险丝。 通过改变熔丝设置，可以改变中央处理单元的特性，从而整个微控制器的特性。

公开(公告)号：WO2013048726A1

公开(公告)日：2013-04-04

申请号：PCT/US2012/054733

申请日：2012-09-12

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  BOWLING, Stephen ,  WOJEWODA, Igor

Inventor： BOWLING, Stephen ,  WOJEWODA, Igor

IPC: G06F1/14 ,  G06F1/32

CPC classification number: G06F1/14 ,  G06F1/3243 ,  G06F1/3287 ,  G06F15/7814 ,  G06F15/7853 ,  Y02D10/152 ,  Y02D10/171

Abstract: A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: - a timer being clocked by an independent clock signal; - a comparator coupled with a timer register of said timer and having an output generating an output signal; - an event register coupled with said comparator; - a delta time register; and - an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register.

Abstract translation: 微控制器具有中央处理单元（CPU），多个外围设备和可编程调度器单元，其具有： - 由独立时钟信号计时的定时器; - 与所述定时器的定时器寄存器耦合并具有产生输出信号的输出的比较器; - 与所述比较器耦合的事件寄存器; - 增量时间寄存器 以及 - 由比较器的输出信号和第一和第二输入和输出控制的算术逻辑单元，其中第一输入与定时器寄存器或事件寄存器耦合，第二输入与增量时间寄存器耦合， 输出与事件寄存器耦合。

公开(公告)号：WO2008073883A3

公开(公告)日：2008-08-21

申请号：PCT/US2007086963

申请日：2007-12-10

Applicant: MICROCHIP TECH INC ,  SIMMONS MICHAEL ,  WOJEWODA IGOR

Inventor： SIMMONS MICHAEL ,  WOJEWODA IGOR

IPC: G06F9/445 ,  H03K3/037

CPC classification number: G06F1/3203 ,  G06F1/24

Abstract: A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a "low power state wake-up and restore" signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.

Abstract translation: 半导体集成电路器件在从低功率模式退出时唤醒并重新初始化逻辑电路，以恢复内部寄存器的先前逻辑状态而不干扰当时存在的输入 - 输出（I / O）配置控制和数据状态 进入低功耗模式。 因此，先前在低功率模式下不分配连接到半导体集成电路器件的其他器件的操作。 一旦半导体集成电路器件的所有内部逻辑和寄存器都被重新初始化，就会发出“低功耗状态唤醒和恢复”信号。 该信号指示在集成电路装置进入低功率模式时存储在I / O保持器单元中的I / O配置控制和数据状态已经恢复，并且控制可以返回到逻辑电路和/或内部 半导体集成电路器件的寄存器。

公开(公告)号：WO2006091468A3

公开(公告)日：2006-12-21

申请号：PCT/US2006005462

申请日：2006-02-16

Applicant: MICROCHIP TECH INC ,  MASGRAS CRISTIAN P ,  PYSKA MICHAEL ,  BOLES EDAWRD BRIAN ,  TRIECE JOSEPH W ,  WOJEWODA IGOR ,  CHEN MEI-LING

Inventor： MASGRAS CRISTIAN P ,  PYSKA MICHAEL ,  BOLES EDAWRD BRIAN ,  TRIECE JOSEPH W ,  WOJEWODA IGOR ,  CHEN MEI-LING

IPC: G06F11/27 ,  G11C29/46

CPC classification number: G01R31/31701 ,  G06F11/273 ,  G11C29/003 ,  G11C29/46

Abstract: A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.

Abstract translation: 特殊模式键匹配比较模块具有N个存储元件和特殊模式键匹配比较器。 N个存储元件累积串行数据流，然后确定数字设备是否应以正常用户模式，公共编程模式或特定专用测试模式运行。 为了减少意外解码错误测试或编程模式的可能性，数据流具有足够大数目的N位以显着降低错误解码的可能性。 为了进一步降低意外解码编程或测试模式的可能性，如果在N位串行数据流的累积期间检测到少于或多于N个时钟，则可以重置特殊模式密钥匹配比较模块。 特殊模式键匹配数据模式可以表示正常用户模式，公共编程模式和特定的私人制造商测试模式。