公开(公告)号：WO2007042336A2

公开(公告)日：2007-04-19

申请号：PCT/EP2006064298

申请日：2006-07-14

Applicant: ST MICROELECTRONICS SRL ,  COMBI CHANTAL ,  VIGNA BENEDETTO ,  ZIGLIOLI FEDERICO GIOVANNI ,  BALDO LORENZO ,  MAGUGLIANI MANUELA ,  LASALANDRA ERNESTO ,  RIVA CATERINA

Inventor： COMBI CHANTAL ,  VIGNA BENEDETTO ,  ZIGLIOLI FEDERICO GIOVANNI ,  BALDO LORENZO ,  MAGUGLIANI MANUELA ,  LASALANDRA ERNESTO ,  RIVA CATERINA

IPC: B81B7/02

CPC classification number: B81B7/0061 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C1/0023 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/3025 ,  H04R1/04 ,  H04R19/005 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In a substrate-level assembly (22), a device substrate (20) of semiconductor material has a top face (20a) and houses a first integrated device (1; 16), in particular provided with a buried cavity (3), formed within the device substrate (20), and with a membrane (4), suspended over the buried cavity (3) in the proximity of the top face (20a). A capping substrate (21) is coupled to the device substrate (20) above the top face (20a) so as to cover the first integrated device (1; 16), in such a manner that a first empty space (25) is provided above the membrane (4). Electrical-contact elements (28a, 28b) electrically connect the integrated device (1; 16) with the outside of the substrate-level assembly (22). In one embodiment, the device substrate (20) integrates at least a further integrated device (1', 10) provided with a respective membrane (4'); and a further empty space (25'), fluidically isolated from the first empty space (25), is provided over the respective membrane (4') of the further integrated device (1', 10).

Abstract translation: 在衬底级组件（22）中，半导体材料的器件衬底（20）具有顶面（20a）并容纳第一集成器件（1; 16），所述第一集成器件特别设置有埋入腔（3） 在器件衬底（20）内并且具有在顶面（20a）附近悬置在掩埋腔（3）上的膜（4）。 封盖衬底（21）在顶面（20a）上方与器件衬底（20）耦合，以便以这样的方式覆盖第一集成器件（1; 16）：提供第一空的空间（25） 在膜（4）上方。 电接触元件（28a，28b）将集成装置（1; 16）与衬底级组件（22）的外部电连接。 在一个实施例中，所述装置基底（20）集成了至少另一个集成装置（1'，10），所述集成装置设置有相应的膜（4'）; 并且在另一集成装置（1'，10）的相应的膜（4'）上设置与第一空的空间（25）流体隔离的另一个空的空间（25'）。

公开(公告)号：WO2007113878A1

公开(公告)日：2007-10-11

申请号：PCT/IT2006/000229

申请日：2006-04-06

Applicant: STMICROELECTRONICS S.R.L. ,  RIVA, Caterina ,  MURARI, Bruno ,  FRATTINI, Giovanni

Inventor： RIVA, Caterina ,  MURARI, Bruno ,  FRATTINI, Giovanni

IPC: G11B9/00

CPC classification number: G11B9/1409 ,  B82Y10/00 ,  G11B9/14

Abstract: Described herein is a process for manufacturing an interaction structure for a storage medium, which envisages forming a first interaction head provided with a first conductive region having a sub-lithographic smaller dimension (W 1 ). The step of forming a first interaction head (7) envisages: forming on a surface (14) a first delimitation region (15) having a side wall; depositing a conductive portion (16b) having a deposition thickness substantially matching the sub- lithographic smaller dimension (W 1 ) on the side wall; and then defining the conductive portion. The sub- lithographic smaller dimension (W 1 ) is between 1 and 50 nm, preferably 20 nm.

Abstract translation: 这里描述的是用于制造用于存储介质（4）的相互作用结构（6）的方法，其设想形成具有第二导电区域（22）的第一相互作用头部（7），所述第一导电区域具有次光刻尺寸较小（Wi） 。 形成第一相互作用头（7）的步骤设想：在表面（14）上形成具有侧壁（15b）的第一限定区域（15）; 在所述侧壁（15b）上沉积具有基本上与所述亚光刻较小尺寸（Wi）匹配的沉积厚度的导电部分（16b）; 然后限定导电部分。 亚光刻尺寸较小（Wi）在1至50nm之间，优选20nm。

公开(公告)号：WO2012085296A1

公开(公告)日：2012-06-28

申请号：PCT/EP2011/074045

申请日：2011-12-23

Applicant: STMICROELECTRONICS S.R.L. ,  PACI, Dario ,  MORELLI, Marco ,  RIVA, Caterina

Inventor： PACI, Dario ,  MORELLI, Marco ,  RIVA, Caterina

IPC: G01R33/00 ,  G01R33/09

CPC classification number: G01R33/0011 ,  B82Y25/00 ,  G01R33/093 ,  H01L43/12

Abstract: An integrated magnetoresistive device, where a substrate (17) of semiconductor material is covered, on a first surface (19), by an insulating layer (18). A magnetoresistor (26) of ferromagnetic material extends in the insulating layer and defines a sensitivity plane of the sensor. A concentrator (34) of ferromagnetic material including at least one arm (34a), extending in a transversal direction to the sensitivity plane and vertically offset to the magnetoresistor (26). In this way, magnetic flux lines directed perpendicularly to the sensitivity plane are concentrated and deflected so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.

Abstract translation: 通过绝缘层（18）在第一表面（19）上覆盖半导体材料的衬底（17）的集成磁阻器件。 铁磁材料的磁阻（26）在绝缘层中延伸并限定传感器的灵敏度平面。 铁磁材料的集中器（34）包括至少一个臂（34a），沿着横向方向延伸到灵敏度平面并垂直偏移到磁电阻（26）。 以这种方式，垂直于灵敏度平面指向的磁通线被集中和偏转，以便产生指向与灵敏平面平行的方向的磁场分量。

公开(公告)号：WO2007113878A8

公开(公告)日：2008-06-12

申请号：PCT/IT2006000229

申请日：2006-04-06

Applicant: ST MICROELECTRONICS SRL ,  RIVA CATERINA ,  MURARI BRUNO ,  FRATTINI GIOVANNI

Inventor： RIVA CATERINA ,  MURARI BRUNO ,  FRATTINI GIOVANNI

IPC: G11B9/00

CPC classification number: G11B9/1409 ,  B82Y10/00 ,  G11B9/14

Abstract: Described herein is a process for manufacturing an interaction structure for a storage medium, which envisages forming a first interaction head provided with a first conductive region having a sub-lithographic smaller dimension (W 1 ). The step of forming a first interaction head (7) envisages: forming on a surface (14) a first delimitation region (15) having a side wall; depositing a conductive portion (16b) having a deposition thickness substantially matching the sub- lithographic smaller dimension (W 1 ) on the side wall; and then defining the conductive portion. The sub- lithographic smaller dimension (W 1 ) is between 1 and 50 nm, preferably 20 nm.

Abstract translation: 本文描述了一种制造用于存储介质的相互作用结构的方法，其设想形成具有次平版印刷尺寸较小的第一导电区域的第一相互作用头（W1＆lt; 1＆gt;）。 形成第一相互作用头（7）的步骤设想：在表面（14）上形成具有侧壁的第一定界区域（15）; 沉积具有基本上与侧面壁上的亚光刻较小尺寸（W 1> 1）相匹配的沉积厚度的导电部分（16b）; 然后限定导电部分。 亚光刻尺寸较小（W 1 N 1）在1至50nm之间，优选20nm。

公开(公告)号：WO2007042336A3

公开(公告)日：2007-04-19

申请号：PCT/EP2006/064298

申请日：2006-07-14

Applicant: STMicroelectronics S.r.l. ,  COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

Inventor： COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

IPC: B81B7/02 ,  B81B7/00

Abstract: In a substrate-level assembly (22), a device substrate (20) of semiconductor material has a top face (20a) and houses a first integrated device (1; 16), in particular provided with a buried cavity (3), formed within the device substrate (20), and with a membrane (4), suspended over the buried cavity (3) in the proximity of the top face (20a). A capping substrate (21) is coupled to the device substrate (20) above the top face (20a) so as to cover the first integrated device (1; 16), in such a manner that a first empty space (25) is provided above the membrane (4). Electrical-contact elements (28a, 28b) electrically connect the integrated device (1; 16) with the outside of the substrate-level assembly (22). In one embodiment, the device substrate (20) integrates at least a further integrated device (1', 10) provided with a respective membrane (4'); and a further empty space (25'), fluidically isolated from the first empty space (25), is provided over the respective membrane (4') of the further integrated device (1', 10).

公开(公告)号：IT8364284V0

公开(公告)日：1983-05-12

申请号：IT6428483

申请日：1983-05-12

Applicant: DALLA RIVA CATERINA GUGLIELMI

IPC: A01K20060101 ,  A01K