公开(公告)号：WO2012177488A3

公开(公告)日：2013-03-14

申请号：PCT/US2012042495

申请日：2012-06-14

Applicant: QUALCOMM MEMS TECHNOLOGIES INC ,  SASAGAWA TERUO

Inventor： SASAGAWA TERUO

IPC: B81B7/00

CPC classification number: B81B7/0058 ,  B81C2203/0109 ,  B81C2203/0118

Abstract: This disclosure provides systems, methods and apparatus for a MEMS device. In one aspect, an electromechanical systems apparatus includes a substrate, a stationary electrode positioned over the substrate, a movable electrode spaced from the stationary electrode by a gap, and at least one support structure extending above the movable electrode. The support structure includes an inorganic dielectric layer and a polymer layer.

Abstract translation: 本公开提供了用于MEMS器件的系统，方法和装置。 一方面，机电系统装置包括基板，位于基板上方的固定电极，通过间隙与固定电极隔开的可动电极以及在可动电极上方延伸的至少一个支撑结构。 支撑结构包括无机介电层和聚合物层。

公开(公告)号：WO2012177488A2

公开(公告)日：2012-12-27

申请号：PCT/US2012/042495

申请日：2012-06-14

Applicant: QUALCOMM MEMS TECHNOLOGIES, INC. ,  SASAGAWA, Teruo

Inventor： SASAGAWA, Teruo

IPC: B81C1/00

CPC classification number: B81B7/0058 ,  B81C2203/0109 ,  B81C2203/0118

Abstract: This disclosure provides systems, methods and apparatus for a MEMS device. In one aspect, an electromechanical systems apparatus includes a substrate, a stationary electrode positioned over the substrate, a movable electrode spaced from the stationary electrode by a gap, and at least one support structure extending above the movable electrode. The support structure includes an inorganic dielectric layer and a polymer layer.

Abstract translation: 本公开提供了用于MEMS器件的系统，方法和装置。 一方面，机电系统装置包括基板，位于基板上方的固定电极，通过间隙与固定电极隔开的可动电极以及在可动电极上方延伸的至少一个支撑结构。 支撑结构包括无机介电层和聚合物层。

公开(公告)号：WO2007123820A3

公开(公告)日：2008-01-03

申请号：PCT/US2007008564

申请日：2007-04-05

Applicant: QUALCOMM INC ,  SASAGAWA TERUO ,  KOGUT LIOR ,  TUNG MING-HAU

Inventor： SASAGAWA TERUO ,  KOGUT LIOR ,  TUNG MING-HAU

IPC: B81C1/00

CPC classification number: B81B3/0008 ,  G02B26/001

Abstract: Methods of making MEMS devices including interferometric modulators involve depositing various layers, including stationary layers, movable layers and sacrificial layers, on a substrate. A non-planar surface is formed on one or more layers by flowing an etchant through a permeable layer. In one embodiment the non-planar surface is formed on a sacrificial layer. A movable layer formed over the non-planar surface of the sacrificial layer results in a non-planar interface between the sacrificial and movable layers. Removal of the sacrificial layer results in a released MEMS device having reduced contact area between the movable and stationary layers when the MEMS device is actuated. The reduced contact area results in lower adhesion forces and reduced stiction during actuation of the MEMS device. These methods may be used to manufacture released and unreleased interferometric modulators.

Abstract translation: 制造包括干涉式调制器的MEMS器件的方法包括在衬底上沉积包括固定层，可移动层和牺牲层的各种层。 通过使蚀刻剂流过可渗透层而在一个或多个层上形成非平面表面。 在一个实施例中，非平面表面形成在牺牲层上。 形成在牺牲层的非平面表面上的可移动层导致牺牲层和可移动层之间的非平面界面。 牺牲层的去除导致释放的MEMS器件在MEMS器件致动时具有减小可移动层和固定层之间的接触面积。 减小的接触面积导致MEMS器件的致动期间较低的粘附力和降低的静摩擦力。 这些方法可用于制造释放和未释放的干涉式调制器。

公开(公告)号：WO2007078495A3

公开(公告)日：2007-12-06

申请号：PCT/US2006045925

申请日：2006-11-30

Applicant: QUALCOMM INC ,  WANG CHUN-MING ,  LAN JEFFREY ,  SASAGAWA TERUO

Inventor： WANG CHUN-MING ,  LAN JEFFREY ,  SASAGAWA TERUO

IPC: B81B3/00 ,  G02B26/00 ,  G02B26/08

CPC classification number: B81C1/00047 ,  B81B2201/047 ,  B81C2201/0108 ,  B81C2201/0111 ,  G02B26/001

Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer. Another embodiment provides a method for making an interferometric modulator that includes providing a substrate, depositing a first electrically conductive material over at least a portion of the substrate, depositing a sacrificial material over at least a portion of the first electrically conductive material, depositing an insulator over the substrate and adjacent to the sacrificial material to form a support structure, and depositing a second electrically conductive material over at least a portion of the sacrificial material, the sacrificial material being removable by heat-vaporization to thereby form a cavity between the first electrically conductive layer and the second electrically conductive layer.

Abstract translation: MEMS器件（诸如干涉式调制器）可以使用含有可热蒸发聚合物的牺牲层来制造，以在可移动层和衬底之间形成间隙。 一个实施例提供了一种制造MEMS器件的方法，该方法包括：在衬底上沉积聚合物层;在聚合物层上形成导电层;以及蒸发至少一部分聚合物层，以在衬底和电气之间形成空腔 导电层。 另一个实施例提供了一种制造干涉式调制器的方法，该方法包括提供衬底，在衬底的至少一部分上沉积第一导电材料，在第一导电材料的至少一部分上沉积牺牲材料，沉积绝缘体 在衬底上并且与牺牲材料相邻以形成支撑结构，以及在牺牲材料的至少一部分上沉积第二导电材料，牺牲材料通过热汽化可去除，从而在第一电气 导电层和第二导电层。

公开(公告)号：WO2007120886A2

公开(公告)日：2007-10-25

申请号：PCT/US2007/009274

申请日：2007-04-12

Applicant: QUALCOMM INCORPORATED ,  SASAGAWA, Teruo ,  KOGUT, Lior

Inventor： SASAGAWA, Teruo ,  KOGUT, Lior

CPC classification number: B81B3/001 ,  B81B2201/047 ,  B81C2201/0115 ,  G02B26/001

Abstract: A microelectromechanical device (MEMS) utilizing a porous electrode surface for reducing stiction is disclosed. In one embodiment, a microelectromechanical device is an interferometric modulator 80 that includes a transparent electrode 81 having a first surface 81a; and a movable reflective electrode 82 with a second surface 82a facing the first surface 81a. The movable reflective electrode 82 is movable between a relaxed and actuated (collapsed) position. An aluminum layer is provided on either the first or second surface. The aluminum layer is then anodized to provide an aluminum oxide layer 83 which has a porous surface 83a. The porous surface 83a, in the actuated position, decreases contact area between the electrodes 81 and 82, thus reducing stiction.

Abstract translation: 公开了一种利用多孔电极表面降低静摩擦力的微机电装置（MEMS）。 在一个实施例中，微机电装置是干涉式调制器80，其包括具有第一表面81a的透明电极81; 以及具有面向第一表面81a的第二表面82a的可移动反射电极82。 可移动反射电极82可在松弛和致动（折叠）位置之间移动。 在第一或第二表面上提供铝层。 然后将铝层阳极氧化以提供具有多孔表面83a的氧化铝层83。 处于致动位置的多孔表面83a减小了电极81和82之间的接触面积，从而减小了静电。

公开(公告)号：WO2007022479A1

公开(公告)日：2007-02-22

申请号：PCT/US2006/032516

申请日：2006-08-17

Applicant: QUALCOMM MEMS TECHNOLOGIES, INC. ,  QUI, Chengbin ,  SASAGAWA, Teruo ,  TUNG, Ming-Hau ,  WANG, Chun-Ming ,  ZEE, Stephen

Inventor： QUI, Chengbin ,  SASAGAWA, Teruo ,  TUNG, Ming-Hau ,  WANG, Chun-Ming ,  ZEE, Stephen

IPC: B81C1/00

CPC classification number: G02B26/0841 ,  B81B3/0072 ,  B81B2201/047 ,  B81B2203/0163 ,  B81B2203/019 ,  B81B2203/0307 ,  B81B2203/053 ,  B81C1/00142 ,  B81C1/00666 ,  B81C2201/0167 ,  G02B26/001 ,  Y10S359/90

Abstract: Certain MEMS devices include layers patterned to have tapered edges. One method for forming layers having tapered edges includes the use of an etch leading layer. Another method for forming layers having tapered edges includes the deposition of a layer in which the upper portion is etchable at a faster rate than the lower portion. Another method for forming layers having tapered edges includes the use of multiple iterative etches. Another method for forming layers having tapered edges includes the use of a liftoff mask layer having an aperture including a negative angle, such that a layer can be deposited over the liftoff mask layer and the mask layer removed, leaving a structure having tapered edges.

Abstract translation: 某些MEMS器件包括被图案化以具有渐缩边缘的层。 用于形成具有渐缩边缘的层的一种方法包括使用蚀刻引导层。 用于形成具有锥形边缘的层的另一种方法包括沉积一层，其中上部可以比下部更快的速度进行刻蚀。 用于形成具有渐缩边缘的层的另一种方法包括使用多个迭代蚀刻。 用于形成具有锥形边缘的层的另一种方法包括使用具有包括负角度的孔的剥离掩模层，使得可以在剥离掩模层上沉积一层，并且去除掩模层，留下具有渐缩边缘的结构。

公开(公告)号：WO2012067826A3

公开(公告)日：2012-08-23

申请号：PCT/US2011058983

申请日：2011-11-02

Applicant: QUALCOMM MEMS TECHNOLOGIES INC ,  BITA ION ,  LI KEBIN ,  RAO RASHMI ,  SASAGAWA TERUO ,  ARBUCKLE BRIAN W ,  CUMMINGS WILLIAM

Inventor： BITA ION ,  LI KEBIN ,  RAO RASHMI ,  SASAGAWA TERUO ,  ARBUCKLE BRIAN W ,  CUMMINGS WILLIAM

IPC: G02B6/00 ,  F21V8/00

CPC classification number: G02B26/001 ,  G02B6/005 ,  Y10T29/49826

Abstract: This disclosure provides systems, methods and apparatus for providing illumination by using a light guide (120) to distribute light. In one aspect, a passivation layer (110) is attached to the light guide of an illumination device. The passivation layer may be an optically transparent moisture barrier and may have a thickness and refractive index which allows it to function as an anti - reflective coating. The passivation layer may protect moisture - sensitive underlying features, such as metallized light turning features (140) that may be present in the light guide. The light turning features may be configured to redirect light out of the light guide. In some implementations, the redirected light may be applied to illuminate a display.

Abstract translation: 本公开提供了通过使用光导（120）分配光来提供照明的系统，方法和装置。 在一个方面，钝化层（110）附接到照明装置的光导。 钝化层可以是光学透明的水分屏障，并且可以具有允许其用作抗反射涂层的厚度和折射率。 钝化层可以保护湿气敏感的底层特征，例如可能存在于光导中的金属化的光转动特征（140）。 光转向特征可以被配置为将光重定向到光导中。 在一些实施方案中，可以应用重定向的光来照亮显示器。

公开(公告)号：WO2012061205A1

公开(公告)日：2012-05-10

申请号：PCT/US2011/058145

申请日：2011-10-27

Applicant: QUALCOMM MEMS TECHNOLOGIES, INC. ,  SASAGAWA, Teruo ,  FENNELL, Leonard, Eugene

Inventor： SASAGAWA, Teruo ,  FENNELL, Leonard, Eugene

IPC: H01H59/00 ,  H01L21/768 ,  B81B3/00

CPC classification number: B81B3/001 ,  B81B2201/042 ,  G02B26/001

Abstract: This disclosure provides systems, methods, and apparatus for producing roughness in an electromechanical device by nucleation under plasma CVD conditions. In one aspect, a substrate and at least a first layer are provided. The disclosure further provides gas phase nucleating particles under plasma CVD conditions and depositing a first layer, where the particles are incorporated into the first layer to create roughness in the first layer. The roughness may be transferred to a second layer by conformal deposition of the second layer over the first layer. The roughness of the second layer corresponds to the roughness of the first layer, where the first layer has a roughness greater than or equal to about 20 Å root mean square (RMS).

Abstract translation: 本公开提供了在等离子体CVD条件下通过成核产生机电装置中的粗糙度的系统，方法和装置。 在一个方面，提供了一个基底和至少一个第一层。 本公开进一步在等离子体CVD条件下提供气相成核颗粒并沉积第一层，其中颗粒结合到第一层中以在第一层中产生粗糙度。 粗糙度可以通过在第一层上的第二层的共形沉积而转移到第二层。 第二层的粗糙度对应于第一层的粗糙度，其中第一层具有大于或等于约均方根（RMS）的粗糙度。

公开(公告)号：WO2009036215A3

公开(公告)日：2009-06-11

申请号：PCT/US2008076077

申请日：2008-09-11

Applicant: QUALCOMM MEMS TECHNOLOGIES INC ,  YAN XIAOMING ,  HO CHOK ,  HEALD DAVID ,  GOUSEV EVGENI ,  HERTZLER BENJAMIN W ,  FLOYD PHILIP ,  SASAGAWA TERUO ,  LONDERGAN ANA ,  BITA ION ,  ZION TODD

Inventor： YAN XIAOMING ,  HO CHOK ,  HEALD DAVID ,  GOUSEV EVGENI ,  HERTZLER BENJAMIN W ,  FLOYD PHILIP ,  SASAGAWA TERUO ,  LONDERGAN ANA ,  BITA ION ,  ZION TODD

IPC: H01L21/311 ,  B01D53/68 ,  H01L21/3213

CPC classification number: H01L21/32135 ,  B01D53/002 ,  B01D2257/11 ,  B01D2257/2027 ,  H01L21/31116

Abstract: A method of fabricating an electonic device which comprises a step of etching a sacrificial layer with an etchant comprising a noble gas fluoride, e.g. Xenon Fluoride (Xe F2). The efficiency of the etching process may be increased in various ways, and the cost of an etching process may be decreased. Unused etchant may be isolated and recirculated during the etching process. Etching byproducts may be collected and removed from the etching system during the etching process. Components of the etchant may be isolated and used to general additional etchant. Either or both of the etchant or the layers being etched may also be optimized for a particular etching process.

Abstract translation: 一种制造电子器件的方法，其包括用包含惰性气体氟化物的蚀刻剂蚀刻牺牲层的步骤，例如， 氟化氙（Xe F2）。 可以以各种方式提高蚀刻工艺的效率，并且可以降低蚀刻工艺的成本。 未蚀刻的蚀刻剂可以在蚀刻过程中被隔离并再循环。 蚀刻副产物可以在蚀刻过程中从蚀刻系统中收集和去除。 蚀刻剂的组分可以被分离并用于一般的另外的蚀刻剂。 蚀刻剂或被蚀刻的层中的任一个或两者也可以针对特定的蚀刻工艺进行优化。

公开(公告)号：WO2009020801A3

公开(公告)日：2009-02-12

申请号：PCT/US2008/071498

申请日：2008-07-29

Applicant: QUALCOMM MEMS TECHNOLOGIES, INC. ,  SASAGAWA, Teruo

Inventor： SASAGAWA, Teruo

IPC: B81B7/00

Abstract: A microelectromechanical systems (MEMS) device includes a substrate (20), an array region (ARRAY), and a peripheral region (INTERCONNECT). The array region (ARRAY) includes a lower electrode (16A, 16B), a movable upper electrode (14), and a cavity (19) between the lower electrode (16A, 16B) and the upper electrode (14). The peripheral region (INTERCONNECT) includes a portion of a layer forming the upper electrode (14) in the array region (ARRAY) and an electrical interconnect (58). The electrical interconnect (58) includes a conductive material (50) electrically connected to at least one of the lower electrode (16A, 16B) and the upper electrode (14). The electrical interconnect (58) is formed of a layer separate from and below the layer forming the upper electrode (14) in the array region (ARRAY). The conductive material (50) is selected from the group consisting of nickel, chromium, copper, and silver.