公开(公告)号：WO2005070106A3

公开(公告)日：2009-01-22

申请号：PCT/US2005000604

申请日：2005-01-10

Applicant: SILICON PIPE INC ,  GRUNDY KEVIN P ,  SEGARAM PARA K

Inventor： GRUNDY KEVIN P ,  SEGARAM PARA K

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1689 ,  G06F12/06 ,  G06F13/4256 ,  G06F2212/1016

Abstract: A memory system (100) having a plurality of memory devices (1071-N) and a memory controller (101 ). The memory devices (1071-N) are coupled to one another in a chain The memory controller (101 ) is coupled to the chain and configured to output a memory access command that is received by each of the memory devices(1071-N) in the chain and that selects a set of two or more of the memory devices (1071-N) to be accessed.

Abstract translation: 具有多个存储器件（1071-N）和存储器控制器（101）的存储器系统（100）。 存储器设备（1071-N）在链路中彼此耦合。存储器控制器（101）耦合到链路并且被配置为输出由每个存储器设备（1071-N）接收的存储器访问命令 并且选择要访问的两个或更多个存储器件（1071-N）的集合。

公开(公告)号：WO2005070106A2

公开(公告)日：2005-08-04

申请号：PCT/US2005/000604

申请日：2005-01-10

Applicant: SILICON PIPE, INC. ,  GRUNDY, Kevin, P. ,  SEGARAM, Para, K.

Inventor： GRUNDY, Kevin, P. ,  SEGARAM, Para, K.

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1689 ,  G06F12/06 ,  G06F13/4256 ,  G06F2212/1016

Abstract: A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.

Abstract translation: 一种具有多个存储器件和存储器控制器的存储器系统。 存储器件在链条中彼此耦合。 存储器控制器耦合到链路并且被配置为输出由链中的每个存储器件接收的存储器访问命令，并且选择要访问的两个或更多个存储器件的一组。

公开(公告)号：WO2005050708A2

公开(公告)日：2005-06-02

申请号：PCT/US2004/038286

申请日：2004-11-15

Applicant: SILICON PIPE, INC. ,  GRUNDY, Kevin, P. ,  WIEDEMANN, William, F. ,  FJELSTAD, Joseph, C.

Inventor： GRUNDY, Kevin, P. ,  WIEDEMANN, William, F. ,  FJELSTAD, Joseph, C.

IPC: H01L

CPC classification number: H05K3/3405 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K1/183 ,  H05K3/308 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0919 ,  H05K2201/092 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/1059 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10727 ,  H05K2201/10734 ,  H01L2924/00

Abstract: Disclosed are stair stepped PCB structures which provide high performance, direct path, via-less interconnections between various elements of an electronic interconnection structure including, among others, IC packages and connectors.

Abstract translation: 公开了楼梯级PCB结构，其提供包括IC封装和连接器在内的电子互连结构的各种元件之间的高性能，直接路径，无通孔互连。

公开(公告)号：WO2005031805A2

公开(公告)日：2005-04-07

申请号：PCT/US2004/031350

申请日：2004-09-24

Applicant: SILICON PIPE, INC. ,  INESSA, Obenhuber ,  FJELSTAD, Joseph, C. ,  SEGARAM, Para, K. ,  GRUNDY, Kevin, P.

Inventor： FJELSTAD, Joseph, C. ,  SEGARAM, Para, K. ,  GRUNDY, Kevin, P.

IPC: H01L

CPC classification number: H01L24/85 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49537 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/32245

Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.

Abstract translation: 具有多个表面的IC封装，用于与互连元件互连，从IC芯片连接到位于其多于一个表面上的封装组件的I / O端子，并且与空间上分离的其它器件或组件互连。

公开(公告)号：WO2003090308A1

公开(公告)日：2003-10-30

申请号：PCT/US2003/012132

申请日：2003-04-17

Applicant: SILICON PIPE, INC.

Inventor： FJELSTAD, Joseph, C. ,  HABA, Belgacem ,  SEGARAM, Para, K.

IPC: H01P3/08

CPC classification number: H01P3/088

Abstract: The dielectric constant and loss tangent of a signal transmission structure is lowered by locating discrete conductors (CDn) used for signal transmission between two shields (130, 140) so as to form cavities (ON, OP) between the discrete conductors and each of the shields. Each cavity is filled with any of a number and/or combination of dielectric supports (110, 120) and/or dielectric materials, including air. The discrete conductors are formed across the cavities so that any exposed surfaces of the discrete conductors are in contact with the dielectric material of the respective cavity.

Abstract translation: 信号传输结构的介电常数和损耗角正切通过将用于信号传输的分立导体（CDn）定位在两个屏蔽件（130,140）之间以便在离散导体之间形成空腔（ON，OP）而降低 盾牌。 每个空腔都填充有电介质支撑件（110,120）和/或介电材料（包括空气）的数量和/或组合中的任何一个。 离散导体跨越空腔形成，使得分立导体的任何暴露表面与相应空腔的电介质材料接触。

公开(公告)号：WO2005036610A3

公开(公告)日：2009-04-30

申请号：PCT/US2004033778

申请日：2004-10-12

Applicant: SILICON PIPE INC ,  OBENHUBER INESSA ,  FJELSTAD JOSEPH C ,  SEGARAM PARA K ,  GRUNDY KEVIN P ,  WIEDEMANN WILLIAM F

Inventor： FJELSTAD JOSEPH C ,  SEGARAM PARA K ,  GRUNDY KEVIN P ,  WIEDEMANN WILLIAM F

IPC: H01L23/02 ,  H01L20060101 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L23/04 ,  H01L23/12 ,  H01L23/13 ,  H01L23/28 ,  H01L23/31 ,  H01L23/34 ,  H01L23/48 ,  H01L23/498 ,  H01L23/52 ,  H01L25/065 ,  H01L29/40

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32188 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A cost effective, high performance, IC package assembly of the present invention comprises stair-stepped layers of redistribution circuits from at least one chip to terminals on any of multiple surfaces and levels of the IC package assembly. Critical path circuits of the assembly have no plated vias and are directly routed from interconnection terminals which are used to interconnect the package to the IC chip terminals by flip chip or wire bond methods.

Abstract translation: 本发明的成本有效，高性能的IC封装组件包括从IC封装组件的多个表面和电平中的任何一个上的至少一个芯片到端子的阶梯层的再分配电路。 组件的关键路径电路没有电镀通孔，并且通过倒装芯片或引线键合方法将互连封装与IC芯片端子互连的互连端直接布线。

公开(公告)号：WO2003094203A3

公开(公告)日：2003-11-13

申请号：PCT/US2003/013524

申请日：2003-04-29

Applicant: SILICON PIPE, INC.

Inventor： FJELSTAD, Joseph, C. ,  SEGARAM, Para, K. ,  HABA, Belgacem

IPC: H04B15/00

Abstract: A direct-connect signaling system (200) including a printed circuit board (205) and first (201A) and second (201B) integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors (203) extend between the first and the second integrated circuit packages suspended above the printed circuit board.

公开(公告)号：WO2003094203A2

公开(公告)日：2003-11-13

申请号：PCT/US2003/013524

申请日：2003-04-29

Applicant: SILICON PIPE, INC.

Inventor： FJELSTAD, Joseph, C. ,  SEGARAM, Para, K. ,  HABA, Belgacem

IPC: H01L

CPC classification number: H05K1/147 ,  H01L23/49805 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0228 ,  H05K1/0237 ,  H05K3/222 ,  H05K2201/10356 ,  H05K2201/10378 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and the second integrated circuit packages suspended above the printed circuit board.

Abstract translation: 一种直接连接信号系统，包括印刷电路板和布置在印刷电路板上的第一和第二集成电路封装。 多个电信号导体在悬挂在印刷电路板上的第一和第二集成电路封装之间延伸。

公开(公告)号：WO2005050708A3

公开(公告)日：2007-04-05

申请号：PCT/US2004038286

申请日：2004-11-15

Applicant: SILICON PIPE INC ,  GRUNDY KEVIN P ,  WIEDEMANN WILLIAM F ,  FJELSTAD JOSEPH C

Inventor： GRUNDY KEVIN P ,  WIEDEMANN WILLIAM F ,  FJELSTAD JOSEPH C

IPC: H05K1/03 ,  H05K1/16 ,  H05K1/18 ,  H05K3/30 ,  H05K3/34 ,  H05K3/46

CPC classification number: H05K3/3405 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K1/183 ,  H05K3/308 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0919 ,  H05K2201/092 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/1059 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10727 ,  H05K2201/10734 ,  H01L2924/00

Abstract: Disclosed are stair stepped PCB structures which provide high performance, direct path, via-less interconnections between various elements of an electronic interconnection structure including, among others, IC packages and connectors.

Abstract translation: 公开了楼梯级PCB结构，其提供包括IC封装和连接器在内的电子互连结构的各种元件之间的高性能，直接路径，无通孔互连。

公开(公告)号：WO2005067684A3

公开(公告)日：2005-07-28

申请号：PCT/US2005/000775

申请日：2005-01-07

Applicant: SILICON PIPE, INC. ,  FJELSTAD, Joseph, C. ,  GRUNDY, Kevin, P.

Inventor： FJELSTAD, Joseph, C. ,  GRUNDY, Kevin, P.

IPC: H01L23/02

Abstract: An IC package substrate having integral ESD protection features and elements and a method for construction of the same are disclosed