公开(公告)号：EP2207089A1

公开(公告)日：2010-07-14

申请号：EP09180314.8

申请日：2009-12-22

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

Inventor： Wang, Kai-Feng ,  Sun, Hong- Xia ,  Zhu, Peng-Fei ,  Wu, Yong-Qiang

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3855

Abstract: An embodiment of a technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. Each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.

Abstract translation: 用于在减少指令冲突的机会的同时从多个功能单元的发布队列中选择用于执行的指令的技术的实施例。 处理器中的每个功能单元可以包括从发布队列中选择特定指令以执行的选择逻辑电路。 为了避免指令冲突，功能单元可以具有可以从指令队列中选择两个指令的选择逻辑电路：一个根据第一选择技术和根据第二选择技术的指令。 然后，通过将由第一选择技术选择的指令与由另一功能单元的选择逻辑电路选择的指令进行比较，可以使用由第二技术选择的指令来代替，否则将产生指令冲突，因为由 第一选择技术与在不同功能单元处选择的指令相同。

公开(公告)号：EP2207089B1

公开(公告)日：2014-08-27

申请号：EP09180314.8

申请日：2009-12-22

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

Inventor： Wang, Kai-Feng ,  Sun, Hong- Xia ,  Zhu, Peng-Fei ,  Wu, Yong-Qiang

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3855