公开(公告)号：EP2202637A1

公开(公告)日：2010-06-30

申请号：EP09180317.1

申请日：2009-12-22

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

Inventor： Wang, Kai-Feng ,  Sun, Hong-Xia ,  Wu, Yong-Qiang

IPC: G06F9/38 ,  G06F1/32

CPC classification number: G06F9/3834 ,  G06F9/3824 ,  G06F9/3855

Abstract: A comparison circuit can reduce the amount of power consumed when searching a load queue or a store queue of a microprocessor. Some embodiments of the comparison circuit use a comparison unit that performs an initial comparison of addresses using a subset of the address bits. If the initial comparison results In a match, a second comparison unit can be enabled to compare another subset of the address bits.

Abstract translation: 比较电路可以减少在搜索微处理器的加载队列或存储队列时消耗的功率量。 比较电路的一些实施例使用比较单元，其使用地址位的子集来执行地址的初始比较。 如果初始比较结果在匹配中，可以使第二比较单元能够比较另一个地址位的子集。

公开(公告)号：EP2202637B1

公开(公告)日：2018-02-07

申请号：EP09180317.1

申请日：2009-12-22

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

Inventor： Wang, Kai-Feng ,  Sun, Hong-Xia ,  Wu, Yong-Qiang

IPC: G06F9/38 ,  G06F1/32

CPC classification number: G06F9/3834 ,  G06F9/3824 ,  G06F9/3855

Abstract: A comparison circuit can reduce the amount of power consumed when searching a load queue or a store queue of a microprocessor. Some embodiments of the comparison circuit use a comparison unit that performs an initial comparison of addresses using a subset of the address bits. If the initial comparison results In a match, a second comparison unit can be enabled to compare another subset of the address bits.

公开(公告)号：EP2207089A1

公开(公告)日：2010-07-14

申请号：EP09180314.8

申请日：2009-12-22

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

Inventor： Wang, Kai-Feng ,  Sun, Hong- Xia ,  Zhu, Peng-Fei ,  Wu, Yong-Qiang

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3855

Abstract: An embodiment of a technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. Each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.

Abstract translation: 用于在减少指令冲突的机会的同时从多个功能单元的发布队列中选择用于执行的指令的技术的实施例。 处理器中的每个功能单元可以包括从发布队列中选择特定指令以执行的选择逻辑电路。 为了避免指令冲突，功能单元可以具有可以从指令队列中选择两个指令的选择逻辑电路：一个根据第一选择技术和根据第二选择技术的指令。 然后，通过将由第一选择技术选择的指令与由另一功能单元的选择逻辑电路选择的指令进行比较，可以使用由第二技术选择的指令来代替，否则将产生指令冲突，因为由 第一选择技术与在不同功能单元处选择的指令相同。

公开(公告)号：EP2207089B1

公开(公告)日：2014-08-27

申请号：EP09180314.8

申请日：2009-12-22

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

Inventor： Wang, Kai-Feng ,  Sun, Hong- Xia ,  Zhu, Peng-Fei ,  Wu, Yong-Qiang

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3855

公开(公告)号：EP2202636A1

公开(公告)日：2010-06-30

申请号：EP09180316.3

申请日：2009-12-22

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

Inventor： Wang, Kai-Feng ,  Sun, Hong-Xia ,  Wu, Yong- Qiang

IPC: G06F9/38 ,  G06F1/32

CPC classification number: G06F9/3844 ,  G06F1/3203 ,  G06F1/3243 ,  G06F9/3804 ,  G06F9/382 ,  Y02D10/152

Abstract: Some microprocessors check branch prediction information in a branch history table and/or a branch target buffer. To check for branch prediction information, a microprocessor can identify which instructions are control flow instructions and which instructions are non control flow instructions. To reduce power consumption in the branch history table and/or branch target buffer, the branch history table and/or branch target buffer can check for branch prediction information corresponding to the control flow Instructions and not the non control flow instructions.

Abstract translation: 一些微处理器检查分支历史表和/或分支目标缓冲器中的分支预测信息。 为了检查分支预测信息，微处理器可以识别哪些指令是控制流程指令，哪些指令是非控制流程指令。 为了降低分支历史表和/或分支目标缓冲器的功耗，分支历史表和/或分支目标缓冲器可以检查与控制流程指令相对应的分支预测信息，而不是非控制流程指令。

公开(公告)号：EP2202635B1

公开(公告)日：2018-11-07

申请号：EP09180315.5

申请日：2009-12-22

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

Inventor： Wang, Kai-Feng ,  Sun, Hong-Xia

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3848

Abstract: A system and method for predicting the execution of a branch of computer-executable Instructions. In an embodiment, a branch predictor may include a program-counter register operable to store a program-counter value and a branch-history register operable to store a branch-history value. Additionally, the branch predictor may include a prediction hash table having a plurality of prediction values each uniquely corresponding to a plurality of memory locations. With these components, the branch predictor may generate a first prediction value that corresponds to the program-counter value and may generate a second prediction value that corresponds to a logical combination of the program-counter value and the branch-history value. With these two prediction values obtained from two different prediction schemas, the branch predictor is better suited to generate an overall prediction value based on the first and second prediction values that is more accurate than a single prediction value based upon a single prediction schema.

公开(公告)号：EP2202635A1

公开(公告)日：2010-06-30

申请号：EP09180315.5

申请日：2009-12-22

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

Inventor： Wang, Kai-Feng ,  Sun, Hong-Xia

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3848

Abstract: A system and method for predicting the execution of a branch of computer-executable Instructions. In an embodiment, a branch predictor may include a program-counter register operable to store a program-counter value and a branch-history register operable to store a branch-history value. Additionally, the branch predictor may include a prediction hash table having a plurality of prediction values each uniquely corresponding to a plurality of memory locations. With these components, the branch predictor may generate a first prediction value that corresponds to the program-counter value and may generate a second prediction value that corresponds to a logical combination of the program-counter value and the branch-history value. With these two prediction values obtained from two different prediction schemas, the branch predictor is better suited to generate an overall prediction value based on the first and second prediction values that is more accurate than a single prediction value based upon a single prediction schema.

Abstract translation: 一种用于预测计算机可执行指令的分支的执行的系统和方法。 在一个实施例中，分支预测器可以包括可操作来存储程序计数器值的程序计数器寄存器和可操作来存储分支历史值的分支历史寄存器。 另外，分支预测器可以包括具有多个预测值的预测哈希表，每个预测值唯一地对应于多个存储位置。 利用这些分量，分支预测器可以生成对应于程序计数器值的第一预测值并且可以生成与程序计数器值和分支历史值的逻辑组合对应的第二预测值。 利用从两个不同预测模式获得的这两个预测值，分支预测器更适合于基于比基于单个预测模式的单个预测值更精确的第一和第二预测值生成总体预测值。