公开(公告)号：WO2011109896A1

公开(公告)日：2011-09-15

申请号：PCT/CA2011/000252

申请日：2011-03-09

Applicant: ATI TECHNOLOGIES ULC ,  TOPACIO, Roden

Inventor： TOPACIO, Roden

IPC: H05K3/36 ,  H05K3/10

CPC classification number: H05K3/3452 ,  H01L21/563 ,  H01L23/28 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2201/2072 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Various circuit boards and methods of manufacturing using the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a solder mask (90) to a side (17) of a circuit board (20) and forming at least one opening (105) in the solder mask (90) leading to the side (17). An underfill (25) is placed on the solder mask (90) so that a portion (100) thereof projects into the at least one opening (105).

Abstract translation: 公开了各种电路板及其制造方法。 一方面，提供了一种制造方法，其包括将焊料掩模（90）施加到电路板（20）的侧面（17）并且形成在所述焊接掩模（90）中的至少一个开口（105），从而导致 侧面（17）。 将底部填充物（25）放置在焊料掩模（90）上，使其一部分（100）突出到至少一个开口（105）中。

公开(公告)号：WO2011029185A1

公开(公告)日：2011-03-17

申请号：PCT/CA2010/001403

申请日：2010-09-09

Applicant: ATI TECHNOLOGIES ULC ,  TOPACIO, Roden R. ,  LOW, Yip Seng

Inventor： TOPACIO, Roden R. ,  LOW, Yip Seng

IPC: H01L21/60 ,  H01L23/488 ,  H05K13/04

CPC classification number: H01L23/49838 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/05624 ,  H01L2924/01039 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first conductor structure on a first side of a semiconductor chip and forming a second conductor structure in electrical contact with the first conductor structure. The second conductor structure is adapted to be coupled to a solder structure and includes a stair arrangement that has at least two treads.

Abstract translation: 公开了各种半导体芯片输入/输出结构及其制造方法。 一方面，提供一种制造方法，其包括在半导体芯片的第一侧上形成第一导体结构，并形成与第一导体结构电接触的第二导体结构。 第二导体结构适于耦合到焊料结构并且包括具有至少两个胎面的阶梯布置。

公开(公告)号：WO2008026077A3

公开(公告)日：2011-03-03

申请号：PCT/IB2007003615

申请日：2007-08-31

Applicant: ATI TECHNOLOGIES ULC ,  MCLELLAN NEIL R ,  CHAN VINCENT K ,  TOPACIO RODEN R

Inventor： MCLELLAN NEIL R ,  CHAN VINCENT K ,  TOPACIO RODEN R

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/48

CPC classification number: H01L21/563 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/3185 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An integrated circuit package includes an encapsulant retention structure located adjacent to a die on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the die. The retention structure placed on the substrate may also serve as a substrate stiffener to maintain mechanical properties of the substrate, allowing use of a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener allows passive electronic components to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, where a larger strip with a plurality of integrated circuit packages is produced industrially and then singulated.

Abstract translation: 集成电路封装包括邻近衬底上的管芯的密封剂保留结构。 该结构允许更大量的密封剂的放置和保持在模具下渗出。 放置在衬底上的保持结构也可以用作衬底加强件，以保持衬底的机械性能，从而允许使用更理想的更薄衬底。 在一个实施例中，在加强件中使用开口和凹槽允许无源电子部件在使用更薄的衬底时保持机械性能。 使用保留壁或加强件允许使用带状矩阵来制造这些集成电路封装，其中具有多个集成电路封装的较大条带在工业上制造然后被分割。

公开(公告)号：WO2009071982A2

公开(公告)日：2009-06-11

申请号：PCT/IB2008003343

申请日：2008-12-04

Applicant: ATI TECHNOLOGIES ULC ,  ATI INT SRL ,  MCLELLAN NEIL ,  LI YUE ,  TOPACIO RODEN ,  CHEUNG TERENCE

Inventor： MCLELLAN NEIL ,  LI YUE ,  TOPACIO RODEN ,  CHEUNG TERENCE

IPC: H01L23/485 ,  H01L21/60 ,  H01L23/525

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/50 ,  H01L23/525 ,  H01L23/5286 ,  H01L24/11 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

Abstract: Various semiconductor chip conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a semiconductor chip. The conductor structure has a first site electrically connected to a first redistribution layer structure and a second site electrically connected to a second redistribution layer structure. A solder structure is formed on the conductor structure.

Abstract translation: 提供各种半导体芯片导体结构及其制造方法。 一方面，提供一种制造方法，其包括在半导体芯片上形成导体结构。 导体结构具有电连接到第一再分配层结构的第一部位和电连接到第二再分配层结构的第二部位。 在导体结构上形成焊料结构。

公开(公告)号：WO2013088263A3

公开(公告)日：2013-06-20

申请号：PCT/IB2012/003096

申请日：2012-12-11

Applicant: ATI TECHNOLOGIES ULC ,  TOPACIO, Roden R. ,  MARTINEZ, Liane ,  LOW, Yip Seng

Inventor： TOPACIO, Roden R. ,  MARTINEZ, Liane ,  LOW, Yip Seng

IPC: H05K1/14 ,  H05K7/20

Abstract: According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package.

公开(公告)号：WO2012142701A1

公开(公告)日：2012-10-26

申请号：PCT/CA2012/000371

申请日：2012-04-23

Applicant: ATI TECHNOLOGIES ULC ,  TOPACIO, Roden ,  WONG, Gabriel

Inventor： TOPACIO, Roden ,  WONG, Gabriel

IPC: H01L21/71 ,  H01L23/488

CPC classification number: H01L24/17 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/33 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/1132 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/01031

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract translation: 公开了一种用于半导体管芯的布线层。 路由层包括将集成电路焊盘与UBM相互连接的迹线。 布线层形成在介电材料层上。 路由层包括布置在UBM下方的导电迹线，以吸收附着到UMB的焊料凸起的应力。 UBM下面的痕迹可保护靠近焊料凸块的基底电介质材料的部分不受应力影响。

公开(公告)号：WO2009071982A3

公开(公告)日：2009-06-11

申请号：PCT/IB2008/003343

申请日：2008-12-04

Applicant: ATI TECHNOLOGIES ULC ,  ATI INTERNATIONAL SRL ,  MCLELLAN, Neil ,  LI, Yue ,  TOPACIO, Roden ,  CHEUNG, Terence

Inventor： MCLELLAN, Neil ,  LI, Yue ,  TOPACIO, Roden ,  CHEUNG, Terence

IPC: H01L23/485 ,  H01L21/60 ,  H01L23/525 ,  H01L23/50 ,  H01L23/528

Abstract: Various semiconductor chip conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a semiconductor chip. The conductor structure has a first site electrically connected to a first redistribution layer structure and a second site electrically connected to a second redistribution layer structure. A solder structure is formed on the conductor structure.

公开(公告)号：WO2008087530A1

公开(公告)日：2008-07-24

申请号：PCT/IB2008/000091

申请日：2008-01-15

Applicant: ATI TECHNOLOGIES ULC ,  ATI INTERNATIONAL SRL ,  TOPACIO, Roden, R. ,  CHAN, Vincent, K.

Inventor： TOPACIO, Roden, R. ,  CHAN, Vincent, K.

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3142 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01322

Abstract: An integrated circuit product includes a die and an insulation layer. The insulation layer is operatively coupled to the die. The insulation layer includes a plurality of bump apertures. The insulation layer also includes an underfill anchor structure. Methods for making such an integrated circuit product are also described.

Abstract translation: 集成电路产品包括管芯和绝缘层。 绝缘层可操作地耦合到管芯。 绝缘层包括多个凸起孔。 绝缘层还包括底部填充锚结构。 还描述了制造这种集成电路产品的方法。

公开(公告)号：WO2013088263A2

公开(公告)日：2013-06-20

申请号：PCT/IB2012003096

申请日：2012-12-11

Applicant: CANADIAN INTELLECTUAL PROPERTY OFFICEATI TECHNOLOGIES ULC ,  TOPACIO RODEN R ,  MARTINEZ LIANE ,  LOW YIP SENG

Inventor： TOPACIO RODEN R ,  MARTINEZ LIANE ,  LOW YIP SENG

IPC: H05K1/14

CPC classification number: H01L23/36 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2924/00

Abstract: According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package.

Abstract translation: 根据一个实施例，一种用于封装封装器件的顶部封装和底部封装之间的封装封装式散热器插入器可以包括位于顶部封装之下的顶部散热器; 在顶部散热器下方的插入器基板; 位于插入器底部下方的底部散热器; 在所述插入器基板和所述顶部散热器之间的第一内插基板金属层; 在所述插入器基板和所述底部散热器之间的第二插入件基板金属层; 以及在第二插入器基板金属层和底部封装之间的插入件焊球。

公开(公告)号：WO2012177450A1

公开(公告)日：2012-12-27

申请号：PCT/US2012/042137

申请日：2012-06-13

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC. ,  TOPACIO, Roden, R. ,  LEE, I-Tseng

Inventor： TOPACIO, Roden, R. ,  LEE, I-Tseng

IPC: H01L23/485 ,  H01L23/31 ,  H01L21/60

CPC classification number: H01L24/03 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05561 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a first polymer film (80) to a side of a semiconductor chip (15 )and forming a first underbump metallization structure (75) with at least a portion on the first polymer film. (80) A second polymer film (118) is applied on the first polymer film (80) with an opening (205) exposing a portion of the first underbump metallization structure (75).

Abstract translation: 公开了各种半导体芯片输入/输出结构及其制造方法。 一方面，提供一种制造方法，其包括将第一聚合物膜（80）施加到半导体芯片（15）的一侧，并且在第一聚合物膜上的至少一部分形成第一底部金属化结构（75） 。 （80）将第二聚合物膜（118）施加在第一聚合物膜（80）上，其中开口（205）露出第一底部金属化结构（75）的一部分。