公开(公告)号：KR101736383B1

公开(公告)日：2017-05-30

申请号：KR1020100074894

申请日：2010-08-03

Applicant: 삼성전자주식회사

Inventor： 송익현 ,  송기환 ,  김진영

IPC: G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C13/00 ,  G11C16/26 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/004

Abstract: 메모리장치의글로벌비트라인프리차지방법이개시된다. 상기방법은메모리셀 어레이에포함된복수의서브어레이들사이에위치한적어도하나의제1프리차지회로를이용하여선택된글로벌비트라인을제1프리차지전압으로프리차지하는단계와, 상기메모리셀 어레이의외부위치하는제2프리차지회로를이용하여상기선택된글로벌비트라인을제2프리차지전압으로프리차지하는단계를포함한다.

Abstract translation: 公开了一种存储器件的全局位线预充电方法。 该方法包括使用位于存储器单元阵列中包括的多个子阵列之间的至少一个第一预充电电路将选定的全局位线预充电到第一预充电电压， 并且使用位于第二预充电电路的第二预充电电路将选定的全局位线预充电至第二预充电电压。

公开(公告)号：KR101461632B1

公开(公告)日：2014-11-13

申请号：KR1020080114216

申请日：2008-11-17

Applicant: 삼성전자주식회사

Inventor： 김진영 ,  송기환

IPC: G11C7/12 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C11/4091 ,  G11C11/4097 ,  G11C2207/002

Abstract: 본 발명은 계층적 비트 라인 구조를 가지는 반도체 메모리 장치를 공개한다. 이 장치는 워드 라인들과 제1 로컬 비트 라인들 각각의 사이에 연결된 복수개의 제1 메모리 셀들 및 상기 워드 라인들과 제2 로컬 비트 라인들 각각의 사이에 연결된 복수개의 제2 메모리 셀들을 구비하는 메모리 셀 어레이, 리드 동작시 제1 센싱 기간에 상기 제1 로컬 비트 라인들 각각을 제1 글로벌 비트 라인들 각각과 연결하고, 제2 센싱 기간에 상기 제2 로컬 비트 라인들 각각을 제2 글로벌 비트 라인들 각각과 연결하는 스위칭 블록, 및 상기 리드 동작시 상기 제1 센싱 기간에 상기 제1 글로벌 비트 라인들 각각의 데이터를 감지하여 증폭하고, 상기 제2 센싱 기간에 상기 제2 글로벌 비트 라인들 각각의 데이터를 감지하여 증폭하는 센싱 블록을 구비하는 것을 특징으로 한다.

公开(公告)号：KR1020110135169A

公开(公告)日：2011-12-16

申请号：KR1020100054922

申请日：2010-06-10

Applicant: 삼성전자주식회사

Inventor： 김진영 ,  송기환

IPC: G11C16/24 ,  G11C16/26

CPC classification number: G11C5/063 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038

Abstract: PURPOSE: A nonvolatile memory device using a resistive element and a memory system including the same are provided to perform an RWW(Read While Write) operation without an error by reducing a power noise. CONSTITUTION: A memory array(110) includes a plurality of memory banks(BANK0-BANK7) arranged in a first direction. Each memory bank is extended in a second direction. Each memory bank includes a nonvolatile memory cell with a variable resistive element whose resistance is varied according to stored data. A write global bit line and a read global bit line are extended in the first direction and are shared by a plurality of memory banks. A write circuit(132,142,152) is connected to the write global bit line and is arranged on the first side of the memory array. A read circuit is connected to the read global bit line and is arranged on the second side of the memory array.

Abstract translation: 目的：提供使用电阻元件的非易失性存储器件和包括该电阻元件的存储器系统，通过降低功率噪声来执行RWW（Read While Write）操作而没有错误。 构成：存储器阵列（110）包括沿第一方向布置的多个存储体（BANK0-BANK7）。 每个存储体在第二方向上延伸。 每个存储体包括具有可变电阻元件的非易失性存储单元，其电阻根据存储的数据而变化。 写全局位线和读全局位线在第一方向上被扩展并由多个存储体共享。 写入电路（132,142,152）连接到写入全局位线并且布置在存储器阵列的第一侧上。 读取电路连接到读取的全局位线并且被布置在存储器阵列的第二侧上。

公开(公告)号：KR1020100095801A

公开(公告)日：2010-09-01

申请号：KR1020090014802

申请日：2009-02-23

Applicant: 삼성전자주식회사

Inventor： 김진영 ,  송기환

IPC: G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4094 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4091

Abstract: PURPOSE: A sense amplifier using a bit line boosting and a semiconductor memory device having the same are provided to maximize the sensing efficiency by pre-amplifying the voltage of the bit line and a complementary bit line. CONSTITUTION: A memory cell array includes a bit line(11), a complementary bit line(12), a memory cell array connected to the bit line and the complementary bit line. A sense amplifier circuit(13) is connected between the bit line and the complementary bit line. A sense amplifier circuit senses the voltage difference between the bit line and the complementary bit line. A plurality of MOS transistors(15,16) comprises the bit line or a gate connected to one of complementary bit lines. MOS transistors boost at least one from the bit line or the complementary bit lines before the sensing operation of the sense amplifier circuit.

Abstract translation: 目的：提供使用位线升压的读出放大器和具有该读出放大器的半导体存储器件，以通过预放大位线和互补位线的电压来最大化感测效率。 构成：存储单元阵列包括位线（11），互补位线（12），连接到位线和互补位线的存储单元阵列。 读出放大器电路（13）连接在位线和互补位线之间。 读出放大器电路感测位线和互补位线之间的电压差。 多个MOS晶体管（15,16）包括位线或连接到互补位线之一的栅极。 在感测放大器电路的感测操作之前，MOS晶体管从位线或互补位线提升至少一个。

公开(公告)号：KR1020100089683A

公开(公告)日：2010-08-12

申请号：KR1020090009033

申请日：2009-02-04

Applicant: 삼성전자주식회사

Inventor： 이재욱 ,  송기환

IPC: G11C11/409 ,  G11C11/4074 ,  G11C11/4063

CPC classification number: G11C11/4096 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4094

Abstract: PURPOSE: A semiconductor memory device including a dynamic memory cell without a capacitor is provided to simplify the structure of a controller for read and/or write operations by applying one fixed level of voltage to a source line. CONSTITUTION: A memory cell array includes a plurality of memory cells with transistors. A transistor includes a floating body which is connected through a plurality of word-lines, a plurality of source-lines, and a plurality of bit-lines. A controller applies a bit-line writing voltage to a selected bit-line from the bit-lines in a write-operating state. The controller applies a second word-line controlling voltage, which is higher than a first word-line controlling voltage, to a selected word-line from the word-lines. The controller stores data in the memory cells by inducing the bipolar junction transistor operation of the memory cells.

Abstract translation: 目的：提供一种包括没有电容器的动态存储单元的半导体存储器件，以通过向源极线施加一个固定电平的电平来简化用于读取和/或写入操作的控制器的结构。 构成：存储单元阵列包括具有晶体管的多个存储单元。 晶体管包括通过多个字线，多个源极线和多个位线连接的浮动体。 控制器在写操作状态下从位线向所选位线施加位线写入电压。 控制器将高于第一字线控制电压的第二字线控制电压从字线施加到所选择的字线。 控制器通过感应存储单元的双极结型晶体管操作来将数据存储在存储单元中。

公开(公告)号：KR1020100040031A

公开(公告)日：2010-04-19

申请号：KR1020080099064

申请日：2008-10-09

Applicant: 삼성전자주식회사

Inventor： 탁남균 ,  송기환

IPC: H01L29/78

CPC classification number: H01L29/7841 ,  H01L21/28114 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/66553 ,  H01L29/7843 ,  H01L29/7846

Abstract: PURPOSE: A transistor, a method for forming the same and a semiconductor memory cell including the same are provided to reduce a gate induced drain leakage current by forming information storage element under space patterns which are located on a gate pattern and on the sidewall of the pattern. CONSTITUTION: A first semiconductor region(80) is formed on a semiconductor substrate(10). Gate patterns(90) are arranged on the first semiconductor region. Spacer patterns(78, 105) are arranged on the sidewall of the gate patterns. The first semiconductor region, a second semiconductor region and a third semiconductor region are successively arranged under the gate pattern and the spacer patterns and around the spacer patterns.

Abstract translation: 目的：提供晶体管，其形成方法和包括该晶体管的半导体存储单元，以通过在位于栅极图案和栅极图案的侧壁上的空间图案之下形成信息存储元件来减小栅极感应漏极泄漏电流 模式。 构成：在半导体衬底（10）上形成第一半导体区域（80）。 栅极图案（90）布置在第一半导体区域上。 间隔图案（78,105）布置在栅极图案的侧壁上。 第一半导体区域，第二半导体区域和第三半导体区域依次布置在栅极图案和间隔物图案之下并且围绕间隔物图案。

公开(公告)号：KR1020090075063A

公开(公告)日：2009-07-08

申请号：KR1020080000826

申请日：2008-01-03

Applicant: 삼성전자주식회사

Inventor： 박덕하 ,  송기환

IPC: G11C11/409 ,  G11C11/401 ,  G11C11/4067

CPC classification number: G11C8/18 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4076 ,  G11C2211/4016

Abstract: A semiconductor memory device and an operation method thereof are provided to reduce the refresh time by refreshing memory cells connected to all word lines at the same time. A semiconductor memory device comprises a memory cell array(50) and a controller. The memory cell array comprises a plurality of memory cells(MC1~MCi). A plurality of memory cells are connected to a plurality of word lines(WL1~WLi), a plurality of bit lines(BL1~BLj) and a plurality of source lines(SL1~SLi). Each memory cell has a floating body transistor. The controller supplies the read control signal to at least one word line and at least one source line in reading. The controller applies the refresh control signal to at least one word line in the refresh operation.

Abstract translation: 提供一种半导体存储器件及其操作方法，通过同时刷新连接到所有字线的存储单元来减少刷新时间。 半导体存储器件包括存储单元阵列（50）和控制器。 存储单元阵列包括多个存储单元（MC1〜MCi）。 多个存储单元连接到多个字线（WL1〜WLi），多个位线（BL1〜BLj）和多条源极线（SL1〜SLi）。 每个存储单元具有浮体晶体管。 控制器将读取控制信号提供给读取中的至少一个字线和至少一个源极线。 控制器将刷新控制信号应用于刷新操作中的至少一个字线。

公开(公告)号：KR1020090036770A

公开(公告)日：2009-04-15

申请号：KR1020070102005

申请日：2007-10-10

Applicant: 삼성전자주식회사

Inventor： 김진영 ,  송기환

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4091

CPC classification number: G11C5/147 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

Abstract: A semiconductor memory device is provided to accurately perform the data read action by adaptively diversifying the source line voltage or the bit line voltage. A source line goal voltage generation unit(510) produces the source line target voltage according to the source line reference voltage and the gate voltage. A comparison unit(520) outputs the voltage signal which is variable by comparing the size of the source line voltage and the source line target voltage. A power source current supply unit(530) controls the power source current supply capacity in response to the output-voltage signal of the comparison unit applied to the gate terminal. A charge pumping part(540) receives many amount of current from the power source current supply unit. The charge pumping part boosts the source line voltage up to the source line target voltage level by charging the capacitor(C1) with current.

Abstract translation: 提供半导体存储器件以通过使源极线电压或位线电压自适应地多样化来精确地执行数据读取动作。 源极线路电压产生单元（510）根据源极线参考电压和栅极电压产生源极线路目标电压。 比较单元（520）通过比较源极线电压和源极线目标电压的大小来输出可变的电压信号。 电源电流供应单元（530）响应于施加到栅极端子的比较单元的输出电压信号来控制电源电流供应容量。 电荷泵送部分（540）从电源电流供应单元接收许多量的电流。 电荷泵送部分通过用电流对电容器（C1）充电，将源极线电压提高到源极线路目标电压电平。

公开(公告)号：KR1020090022748A

公开(公告)日：2009-03-04

申请号：KR1020070088362

申请日：2007-08-31

Applicant: 삼성전자주식회사

Inventor： 탁남균 ,  송기환 ,  윤은정

IPC: H01L21/8242 ,  H01L27/108

Abstract: A method of fabricating one-transistor floating body dram is provided to improve electrical property by minimizing electrical interaction between the increased source area the drain region. A method of fabricating one-transistor floating body dram is comprised of the step: forming a semiconductor film, forming an isolation film, and forming a buried gap. A semiconductor substrate has a cell region and a peripheral area. A sacrificing layer is formed on the cell region and is not formed on the peripheral area of the substrate. A semiconductor film is formed on the sacrificing layer of the cell region and semiconductor substrate of the peripheral area. The isolation film is formed on the semiconductor film and sacrificing layer and restricts a floating body.

Abstract translation: 提供一种制造单晶体体浮体电极的方法，通过最小化漏极区域的增加的源区域之间的电相互作用来改善电性能。 制造单晶体管浮体体的方法包括以下步骤：形成半导体膜，形成隔离膜，形成埋入间隙。 半导体衬底具有单元区域和周边区域。 在单元区域上形成牺牲层，并且不形成在基板的周边区域上。 半导体膜形成在周边区域的单元区域和半导体基板的牺牲层上。 隔离膜形成在半导体膜和牺牲层上并限制浮体。

公开(公告)号：KR1020080058807A

公开(公告)日：2008-06-26

申请号：KR1020060132913

申请日：2006-12-22

Applicant: 삼성전자주식회사

Inventor： 박덕하 ,  송기환 ,  김진영

IPC: G11C11/4074 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4094 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2207/002

Abstract: A capacitor-less dynamic semiconductor memory device and a method of operating the same are provided to suppress memory size increase by using a shared bit line voltage sense amplifier directly sensing and amplifying voltage difference generated in bit lines by controlling a source voltage of floating body transistors of an open bit line structure. A first memory block(311) includes memory cells comprising a floating body transistor having a gate connected to a word line, a drain connected to each of bit lines and a source connected to each of source lines. A second memory block(312) comprises dummy memory cells comprising a floating body transistor having a gate connected to a dummy word line, a drain connected to each of bit lines and a source connected to each of source lines, and an equalizing transistor connected between a gate receiving an equalizing signal and an odd-numbered bit line and an even-numbered bit line adjacent to the odd-numbered bit line. A voltage sense amplification part receives one of bit lines of the first memory block as a first input, and one of the odd-numbered bit line or the adjacent even-numbered bit line of the second memory block as a second input, in response to a bit line selection signal.

Abstract translation: 提供一种无电容动态半导体存储器件及其操作方法，通过使用共享的位线电压读出放大器来抑制存储器大小的增加，直接感测和放大位线中产生的电压差，通过控制浮体晶体管的源极电压 的开放位线结构。 第一存储块（311）包括存储单元，其包括具有连接到字线的栅极的浮动体晶体管，连接到每个位线的漏极和连接到每条源极线的源极。 第二存储器块（312）包括虚拟存储器单元，其包括浮置晶体管，其具有连接到虚拟字线的栅极，连接到每个位线的漏极和连接到每个源极线的源极以及连接在 接收与奇数位线相邻的均衡信号和奇数位线和偶数位线的门。 电压检测放大部分作为第一输入接收第一存储器块的位线之一，并且响应于第二输入，将第二存储器块的奇数位线或相邻偶数位线之一作为第二输入 位线选择信号。