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公开(公告)号：KR100618799B1
公开(公告)日：2006-08-31
申请号：KR1020000010382
申请日：2000-03-02
Applicant: 삼성전자주식회사
IPC: G11C8/12
Abstract: 패킷방식 반도체 메모리장치의 출력 드라이버의 전류 구동능력을 조절하기 위한 전류제어 회로가 개시된다. 상기 전류제어 회로는, 전류제어 인에이블 신호에 응답하여 제1패드의 전압을 전송하는 제1전송수단, 상기 전류제어 인에이블 신호에 응답하여 제2패드의 전압을 전송하는 제2전송수단, 상기 제1전송수단의 출력과 상기 제2전송수단의 출력 사이의 전압을 분배하여 분배전압을 출력하는 전압 분배기, 제1입력단을 통해 입력되는 기준전압과 제2입력단을 통해 입력되는 상기 분배전압을 비교하는 비교기, 및 상기 비교기의 출력에 응답하여 상기 출력드라이버의 전류 구동능력을 조절하기 위한 제어비트들을 발생하는 전류제어 카운터를 구비하고, 특히 상기 전압 분배기는 상기 제1전송수단의 출력의 전하와 상기 제2전송수단의 출력의 전하를 분배(Sharing)하여 상기 분배전압을 발생하는 전하분배형으로 이루어진 것을 특징으로 한다. 따라서 상기 전류제어 회로에서는, 상기 전압 분배기가 전하 분배(Charge sharing)를 이용하는 구조를 가지므로 상기 제1전송수단의 유효저항과 상기 제2전송수단의 유효저항 사이에 차이가 발생하더라도 상기 분배전압에 오프셋(Offset)이 전혀 발생되지 않는다.
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2.发明公开
公开(公告)号：KR1020010009694A
公开(公告)日：2001-02-05
申请号：KR1019990028207
申请日：1999-07-13
Applicant: 삼성전자주식회사
IPC: G11C11/401
CPC classification number: H03K5/1534
Abstract: PURPOSE: A reference voltage regulator is provided to compensate a voltage drop of the reference voltage during a short time without increasing capacity, and also a Rambus DRAM is provided to prevent an output operation speed from being slowed or a mis-operation from being generated by a voltage drop of the reference voltage CONSTITUTION: The device includes an output driver(21), a reference voltage distributor(22), a current controlling circuit(24) includes a reference voltage generator(23a) and a reference voltage compensator(23b). The reference voltage generator generates the reference voltage and supplies the reference voltage to the reference voltage distributor. The reference voltage compensator responds to the output enable signal for compensating a drop of the reference voltage and supplies current to the terminal of the reference voltage generator during a predetermined time.
Abstract translation: 目的：提供参考电压调节器以在短时间内补偿参考电压的电压降而不增加容量，并且还提供Rambus DRAM以防止输出操作速度被减慢或由于产生错误操作 参考电压的压降构成：该装置包括输出驱动器（21），参考电压分配器（22），电流控制电路（24），其包括参考电压发生器（23a）和参考电压补偿器（23b） 。 参考电压发生器产生参考电压，并将参考电压提供给参考电压分配器。 参考电压补偿器响应输出使能信号来补偿参考电压的下降，并在预定时间内向参考电压发生器的端子提供电流。
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公开(公告)号：KR1020010046107A
公开(公告)日：2001-06-05
申请号：KR1019990049722
申请日：1999-11-10
Applicant: 삼성전자주식회사
IPC: H03D13/00
Abstract: PURPOSE: A digital phase detector in a Rambus DRAM is provided to simplify circuit structure without using an integrating circuit and to minimize offset generation by processing signal digitally. CONSTITUTION: A digital phase detector inputs the first and second input signals and detects phase difference between the first input signal and the second input signal. A phase comparator(120) compares the first and second input signals in response to main clock signal and generates up and down signals depending on the comparison result. An up/down signal counter(122) counts the up and down signals in response to the main clock signal and outputs comparison signal which is resulted from comparison of the counted results as phase detection result for the first and second input signals.
Abstract translation: 目的：提供Rambus DRAM中的数字相位检测器，以简化电路结构，而不使用积分电路，并通过数字处理信号最小化偏移生成。 构成：数字相位检测器输入第一和第二输入信号，并检测第一输入信号和第二输入信号之间的相位差。 相位比较器（120）响应于主时钟信号比较第一和第二输入信号，并根据比较结果产生上下信号。 升/降信号计数器（122）响应于主时钟信号对上升和下拉信号进行计数，并将由计数结果的比较产生的比较信号作为第一和第二输入信号的相位检测结果输出。
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公开(公告)号：KR100640562B1
公开(公告)日：2006-10-31
申请号：KR1019990049722
申请日：1999-11-10
Applicant: 삼성전자주식회사
IPC: H03D13/00
Abstract: 램버스 디램에서 디지털 위상 검출기가 공개된다. 제1 및 제2입력 신호를 입력하고, 입력된 제1 및 제2입력 신호의 위상차를 디지털 적으로 검출하는 램버스 디램에서 본 발명에 따른 디지털 위상 검출기는 주 클럭신호에 응답하여 제1 및 제2입력 신호의 위상차를 비교하고, 비교 결과에 상응하여 업신호 및 다운신호를 발생하는 위상 비교기 및 주 클럭신호에 응답하여 업신호 및 다운신호를 각각 카운트하고, 각 카운트된 결과를 비교한 비교신호를 제1 및 제2입력 신호의 위상차 검출 결과로서 출력하는 업/다운 신호 카운터를 구비하는 것을 특징으로 하고, 업/다운 신호 카운터를 이용하여 업신호 및 다운신호를 카운팅하고, 카운팅된 결과를 비교하므로 정확한 비교신호를 발생할 수 있다. 또한, 아날로그 신호로 변환되는 과정 없이 디지털적으로 신호처리가 이루어지므로, 오프셋 발생을 줄일 수 있으며, 종래와 같이 적분회로를 사용하지 않으므로, 디지털 위상 검출회로가 보다 간단히 구현될 수 있으며 동작 방법이 간단해질 수 있는 효과가 있다.
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5.发明授权
公开(公告)号：KR100389914B1
公开(公告)日：2003-07-04
申请号：KR1020000045891
申请日：2000-08-08
Applicant: 삼성전자주식회사
IPC: G11C7/20
CPC classification number: G11C7/1012 , G11C7/1006 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222
Abstract: A semiconductor memory device secures a margin of data setup time and hold time of a data terminal and includes a delay locked loop, an output replica, an output driver, and an output multiplexer. The delay locked loop compares phases of external and feedback clock signals, and generates internal and delayed internal clock signals. The output replica receives memory cell data, generates the feedback control signal and controls load of a line of the feedback control signal to generate the feedback clock signal, responsive to current control signals for controlling current of the data terminal. The output multiplexer delays the memory cell data by a predetermined time in synchronization with the internal clock signal and responsive to the current control signals. The output driver is driven by the current control signals and the delayed memory cell data, and determines voltage level of the data terminal.
Abstract translation: 半导体存储器件确保数据端子的数据建立时间和保持时间的余量，并且包括延迟锁定环，输出副本，输出驱动器和输出多路复用器。 延迟锁定环路比较外部和反馈时钟信号的相位，并生成内部和延迟的内部时钟信号。 响应于用于控制数据终端的电流的电流控制信号，输出副本接收存储器单元数据，产生反馈控制信号并控制反馈控制信号的线的负载以产生反馈时钟信号。 输出多路复用器与内部时钟信号同步地将存储器单元数据延迟预定的时间并且响应于电流控制信号。 输出驱动器由电流控制信号和延迟存储单元数据驱动，并确定数据端子的电压电平。
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Patent Agency Ranking
公开(公告)号：KR100304707B1
公开(公告)日：2001-11-01
申请号：KR1019990028207
申请日：1999-07-13
Applicant: 삼성전자주식회사
IPC: G11C11/401
CPC classification number: H03K5/1534
Abstract: 기준전압의전압강하를짧은시간에보상할수 있는기준전압레귤레이터및 이를구비하는반도체메모리장치가개시된다. 상기기준전압레귤레이터는기준전압발생기및 기준전압보상기를구비한다. 상기기준전압발생기는상기기준전압을발생하고, 상기기준전압보상기는상기기준전압의강하를보상하기위해출력인에이블신호에응답하여소정의시간동안상기기준전압발생기의출력단에전류를공급한다. 또한상기반도체메모리장치는, 상기기준전압발생기및 기준전압보상기를포함하는상기기준전압레귤레이터, 기준전압분배기, 및출력드라이버를구비한다. 상기기준전압분배기는상기기준전압을받아상기출력인에이블신호의활성화동안에복수개의전류구동능력제어신호들에응답하여복수개의게이트인에이블신호들을선택적으로상기기준전압레벨로활성화시킨다. 상기출력드라이버는상기게이트인에이블신호들의선택적인활성화에응답하여전류구동능력이가변되고출력신호를받아출력단으로출력한다.
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公开(公告)号：KR1020010038053A
公开(公告)日：2001-05-15
申请号：KR1019990045861
申请日：1999-10-21
Applicant: 삼성전자주식회사
IPC: G11C5/14
Abstract: PURPOSE: A semiconductor memory device receiving a reference voltage from the external is provided to comprise a reference voltage generator supplying a stable reference voltage to an internal circuit. CONSTITUTION: The semiconductor memory device(201) includes: an input pad(211) where a reference voltage(Vref1) is applied from the external of the semiconductor memory device; a reference voltage generator(221) inputting the reference voltage applied to the input pad and buffering and outputting the reference voltage; an internal voltage converter(231) generating a voltage(V2) of a gate voltage(Vgate) level required in driving an output driver(251) by receiving a reference voltage(Vref2) from the reference voltage generator; an output multiplexer(241) outputting one or some of data(Di) generated in the semiconductor memory device; the output driver inputting the voltage(V2) of the gate voltage level from the internal voltage converter and a signal(q) from the output multiplexer, and outputting the signal(q) to an output pad(261) by being controlled by the voltage(V2) of the gate voltage level.
Abstract translation: 目的：提供从外部接收参考电压的半导体存储器件，其包括向内部电路提供稳定参考电压的参考电压发生器。 构成：半导体存储器件（201）包括：从半导体存储器件的外部施加参考电压（Vref1）的输入焊盘（211） 参考电压发生器（221），输入施加到输入焊盘的参考电压并缓冲并输出参考电压; 内部电压转换器（231），通过从参考电压发生器接收参考电压（Vref2）产生驱动输出驱动器（251）所需的栅极电压（Vgate）电平的电压（V2） 输出多路复用器（241），输出在半导体存储器件中产生的数据（Di）中的一个或一些; 所述输出驱动器从所述内部电压转换器输入所述栅极电压电平的电压（V2）和来自所述输出多路复用器的信号（q），并且通过所述电压控制将所述信号（q）输出到输出焊盘（261） （V2）的栅极电压电平。
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公开(公告)号：KR1020020012711A
公开(公告)日：2002-02-20
申请号：KR1020000045891
申请日：2000-08-08
Applicant: 삼성전자주식회사
IPC: G11C7/20
CPC classification number: G11C7/1012 , G11C7/1006 , G11C7/1051 , G11C7/1072 , G11C7/22 , G11C7/222
Abstract: PURPOSE: A semiconductor memory device is provided, which can assure a data setup time margin and a data hold time margin of a data terminal(DQ) as to a clock signal of the data terminal. CONSTITUTION: A delay locked loop circuit(410) generates an internal clock signal(TCLK) and an internal delay clock signal(TCLK90), by comparing phases of an external clock signal(EXTCLK) and a feedback clock signal(TCLKFB). The internal delay clock signal is provided to an output copy part(420), and the output copy part generates the feedback clock signal by copying the internal delay clock signal. A current control part(430) generates current control signals(ICTRL ), which are selectively activated as to a temperature variation, a process variation and a power supply voltage variation. An output MUX part(440) transmits memory cell data to an output driver(450) in response to the internal clock signal and the current control signals. The output MUX part includes a DA converter/driver, an internal clock signal compensation part and a data transmission part.
Abstract translation: 目的：提供半导体存储器件，其可以确保数据终端（DQ）的数据建立时间裕度和数据保持时间裕度与数据终端的时钟信号。 构成：通过比较外部时钟信号（EXTCLK）和反馈时钟信号（TCLKFB）的相位，延迟锁定环路（410）产生内部时钟信号（TCLK）和内部延迟时钟信号（TCLK90）。 内部延迟时钟信号被提供给输出复制部分（420），并且输出复制部分通过复制内部延迟时钟信号来生成反馈时钟信号。 电流控制部分（430）产生电流控制信号（ICTRL <0：i>），其被选择性地激活温度变化，过程变化和电源电压变化。 响应于内部时钟信号和电流控制信号，输出MUX部分（440）将存储单元数据发送到输出驱动器（450）。 输出MUX部分包括DA转换器/驱动器，内部时钟信号补偿部分和数据传输部分。
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公开(公告)号：KR1020010086686A
公开(公告)日：2001-09-15
申请号：KR1020000010382
申请日：2000-03-02
Applicant: 삼성전자주식회사
IPC: G11C8/12
CPC classification number: G11C5/147
Abstract: PURPOSE: A current control circuit of a packet type semiconductor memory device is provided, which can prevent the generation of an offset in a divided voltage, and where resistances of resistors in a voltage divider can be trimmed accurately. CONSTITUTION: The current control circuit comprises the first transmission gate(T31), the second transmission gate(T32), a voltage divider(V31), a comparator(C31) and a current control counter(D31). The first transmission gate transmits a voltage(VOH) of the first pad in response to a current control enable signal(CCTG), and the second transmission gate transmits a voltage(VOL) of the second pad in response to the current control enable signal. The voltage divider outputs a divided voltage(Vcmp) by dividing a voltage between an output of the first transmission gate and an output of the second transmission gate. The comparator compares a reference voltage(Vref) inputted through the first input terminal with the divided voltage inputted through the second input terminal. The current control counter generates control bits(ICTR0-ICTR5) to control a current driving capability of an output driver in response to an output of the comparator.
Abstract translation: 目的：提供分组型半导体存储器件的电流控制电路，其可以防止产生分压的偏移，并且可以精确地修整分压器中的电阻器的电阻。 构成：电流控制电路包括第一传输门（T31），第二传输门（T32），分压器（V31），比较器（C31）和电流控制计数器（D31）。 第一传输门响应于电流控制使能信号（CCTG）传送第一焊盘的电压（VOH），并且第二传输门响应于电流控制使能信号传输第二焊盘的电压（VOL）。 分压器通过将第一传输门的输出和第二传输门的输出之间的电压除以来输出分压（Vcmp）。 比较器将通过第一输入端子输入的参考电压（Vref）与通过第二输入端子输入的分压进行比较。 电流控制计数器产生控制位（ICTR0-ICTR5），以响应于比较器的输出来控制输出驱动器的电流驱动能力。
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公开(公告)号：KR1020010069001A
公开(公告)日：2001-07-23
申请号：KR1020000001195
申请日：2000-01-11
Applicant: 삼성전자주식회사
IPC: G11C7/00
Abstract: PURPOSE: A semiconductor memory device is provided to reduce power consumption by selectively controlling memory blocks with selected-active signals. CONSTITUTION: The semiconductor memory device includes a plurality of memory blocks(TOP,BOTTOM). The memory blocks are arranged in plurality of memory banks. The memory blocks are classified into a predetermined memory block groups. Each of the memory block group is selectively activated with response to a signal which select memory block groups selectively and a signal which activates the memory blocks. The memory block groups are activated selectively when the memory block group which is not selected is prevented from dissipating power. The signal which selectively selects the memory block groups is one selected from a group consisting of a row pre-charge signal which pre-charges the word line, a bank pre-charge signal which pre-charges a bank and a signal which is activated in a row direction of the bank.
Abstract translation: 目的：提供半导体存储器件以通过选择性地控制具有选择的有源信号的存储器块来降低功耗。 构成：半导体存储器件包括多个存储块（TOP，BOTTOM）。 存储块被布置在多个存储体中。 存储块被分类为预定的存储块组。 响应于选择存储器块组的信号和激活存储器块的信号，选择性地激活每个存储块组。 当未选择的存储块组被阻止耗散功率时，存储块组被选择性地激活。 有选择地选择存储块组的信号是从由预充电字线的行预充电信号，对电池进行预充电的组预充电信号和被激活的信号组成的组中选择的信号 银行的行方向。
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