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公开(公告)号：KR1020120040819A
公开(公告)日：2012-04-30
申请号：KR1020100102270
申请日：2010-10-20
Applicant: 삼성전자주식회사
CPC classification number: G06F1/324 , G06F1/3215 , G06F1/3228 , G06F1/3253 , Y02D10/126 , Y02D10/151 , G06F1/08
Abstract: PURPOSE: A dynamic clock control device in a digital system and a method thereof are provided to reduce the power consumption of system by changing the clock frequency. CONSTITUTION: An AFS(Adaptive Frequency Scaling) control unit(110) determines whether to change the clock frequency of CPU according to CPU operation information. The AFS control unit determines whether to change the clock frequency of bus operation information. A clock control unit(120) generates the clock frequency of the CPU and the bus according to determination of the AFS control unit. The AFS control unit requests the clock control unit to change the clock frequency of the CPU into equal to or greater than a first value.
Abstract translation: 目的：提供数字系统中的动态时钟控制装置及其方法，通过改变时钟频率来降低系统的功耗。 构成：AFS（自适应频率调整）控制单元（110）根据CPU操作信息确定是否改变CPU的时钟频率。 AFS控制单元确定是否改变总线操作信息的时钟频率。 时钟控制单元根据AFS控制单元的确定产生CPU和总线的时钟频率。 AFS控制单元请求时钟控制单元将CPU的时钟频率改变为等于或大于第一值。
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公开(公告)号：KR100240868B1
公开(公告)日：2000-01-15
申请号：KR1019960078024
申请日：1996-12-30
Applicant: 삼성전자주식회사
IPC: H04L1/00
Abstract: 본 발명은 채널크드(channel code)와 반복부분을 효율적인 하나의 채널크드로 대체하여 수신단측에서 에러성능(error performance)이 향상되도록 하는 다중비율 전송 시스템(multi rate transmission system)에 관한 것으로, 콘볼루션 엔코딩에 있어서 반비율의 경우 완전비율에 해당되는 수의 심볼을 발생할 수 있도록 보다 낮은 부호화율(code rate)을 적용하여 콘볼루션 엔코딩을 한다. 그러므로 종래와 같은 반복블록을 사용하지 않게 됨으로 종래의 다중비율 전송 시스템에 비해 에러 성능(error performance)이 향상된다.
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Patent Agency Ranking
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公开(公告)号：KR1020090016086A
公开(公告)日：2009-02-13
申请号：KR1020070080477
申请日：2007-08-10
Applicant: 삼성전자주식회사
IPC: G11C7/22
CPC classification number: G06F1/10
Abstract: An apparatus and a method for preventing a glitch in a clock switching circuit are provided to prevent a system error due to a glitch by preventing the generation of the glitch when a switching operation between clocks is performed in the clock switching circuit. A clock selection unit(220) generates a detect change(Detect_change) signal as an input signal for generating a clock gate(Clk_gate) signal and provides the detect change signal to the clock selection unit. A selection signal management unit(200) changes a Muxsel signal to a selection signal by using a clock gate signal, in order to select a clock to be switched. A clock gate unit(210) generates a clock gate signal by gating the received clock and using a value of the detect change signal as an input signal when receiving the detect change signal. The clock gate unit provides the clock gate signal to the selection signal management unit.
Abstract translation: 提供了一种用于防止时钟切换电路中的毛刺的装置和方法，以防止在时钟切换电路中执行时钟之间的切换操作时通过防止产生毛刺产生的毛刺引起的系统错误。 时钟选择单元（220）产生检测变化（Detect_change）信号作为用于产生时钟门（Clk_gate）信号的输入信号，并将检测改变信号提供给时钟选择单元。 选择信号管理单元（200）通过使用时钟门信号将Muxsel信号改变为选择信号，以选择要切换的时钟。 时钟门单元（210）在接收到检测改变信号时，通过门控接收到的时钟并使用检测改变信号的值作为输入信号来产生时钟门信号。 时钟门单元向选择信号管理单元提供时钟门信号。
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公开(公告)号：KR1020000051271A
公开(公告)日：2000-08-16
申请号：KR1019990001611
申请日：1999-01-20
Applicant: 삼성전자주식회사
Inventor： 권윤주
IPC: H04B1/40
CPC classification number: H04B1/401 , H04B1/1615 , H04M1/73
Abstract: PURPOSE: An interrupt controller is provided to prevent generating of a glitch and to reduce power consumption. CONSTITUTION: An interrupt controller comprises the parts of: a first interrupt generating circuit(10) that generates a first interrupt, which is synchronized and it changes sleep mode to active mode; a second interrupt generating circuit(20) that generates a second interrupt, which changes sleep mode to active mode by receiving first interrupt source request signal as clock signal; a selecting control circuit(30) that generates selection signal to select a first and second interrupt; a clock generating circuit(40) that generates a first clock signal by receiving selection signal and a second clock signal generated from sleep mode and active mode; a clear circuit(50) that initializes a first and second interrupt source circuit; and a selecting circuit(60) that selects one between a first and a second interrupt, responding selection signal.
Abstract translation: 目的：提供中断控制器，以防止产生毛刺并降低功耗。 构成：中断控制器包括以下部分：第一中断产生电路（10），其产生第一中断，其被同步，并且将睡眠模式改变为活动模式; 产生第二中断的第二中断产生电路（20），其通过接收第一中断源请求信号作为时钟信号将睡眠模式改变为活动模式; 选择控制电路（30），其生成选择信号以选择第一和第二中断; 时钟发生电路（40），其通过接收从睡眠模式和活动模式产生的选择信号和第二时钟信号来产生第一时钟信号; 清除电路（50），其初始化第一和第二中断源电路; 以及选择电路（60），其选择第一和第二中断之间的响应选择信号。
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公开(公告)号：KR1019990026452A
公开(公告)日：1999-04-15
申请号：KR1019970048565
申请日：1997-09-24
Applicant: 삼성전자주식회사
Inventor： 권윤주
IPC: H03M13/41
Abstract: 본 발명은 비터비 디코더(Viterbi Decoder)에 관한 것으로서, 구체적으로는 디코딩 과정에서 발생되는 에러를 방지할 수 있는 비터비 디코더에 관한 것으로, 구비된 가산비교선택부(220)에 트래이스백 초기화 제어부(400)를 구비하여 디코딩시에 매 프레임 마다 '0'에서 시작하여 '0'으로 종료되게 하므로서 종래의 경우 디코딩시에 후단 부분에서 에러가 발생될 수 있는 경우가 방지된다.
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