公开(公告)号：KR101725222B1

公开(公告)日：2017-04-11

申请号：KR1020110134000

申请日：2011-12-13

Applicant: 삼성전자주식회사

Inventor： 최재형 ,  박기연 ,  김준 ,  유차영 ,  김윤수 ,  권호준 ,  강상열

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L28/92

Abstract: 캐패시터의하부전극의변형을방지할수 있는반도체소자의제조방법을개시한다. 본발명에따른반도체소자의제조방법은, 몰드층및 몰드층상에배치되는지지대층을가지는반도체기판을준비하는단계, 몰드층및 지지대층을관통하는복수의홀들을형성하는단계, 복수의홀들내에복수의하부전극들을형성하는단계, 몰드층의적어도일부를제거하여, 복수의하부전극들의적어도일부분을노출시키는단계, 복수의하부전극들의노출면으로부터복수의하부전극들의일부분을제거하는단계, 복수의하부전극들상에유전층및 상부전극층을순차적으로형성하는단계를포함한다.

Abstract translation: 公开了一种制造能够防止电容器的下电极变形的半导体器件的方法。 根据本发明的制造半导体器件的方法包括以下步骤：准备具有模层和设置在模层上的支撑层的半导体衬底，形成穿过模层和支撑层的多个孔， 通过去除模制层的至少一部分来暴露多个下电极的至少一部分，从多个下电极的暴露表面去除多个下电极的一部分， 并且在多个下电极上依次形成电介质层和上电极层。

公开(公告)号：KR101944479B1

公开(公告)日：2019-01-31

申请号：KR1020120122989

申请日：2012-11-01

Applicant: 삼성전자주식회사

Inventor： 김형수 ,  이진수 ,  권호준 ,  박동균 ,  이지승 ,  최영석

IPC: H01L27/108 ,  H01L21/8242

公开(公告)号：KR1020130067136A

公开(公告)日：2013-06-21

申请号：KR1020110134000

申请日：2011-12-13

Applicant: 삼성전자주식회사

Inventor： 최재형 ,  박기연 ,  김준 ,  유차영 ,  김윤수 ,  권호준 ,  강상열

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L28/92

Abstract: PURPOSE: A method of manufacturing a semiconductor device is provided to improve the degree of integration by preventing the deformation of a lower electrode. CONSTITUTION: A semiconductor substrate with a support layer(500) is prepared. A mold layer(400) is arranged on the support layer. A plurality of holes pass through the mold layer and the support layer. A plurality of lower electrodes(600) are formed in the plurality of holes. A dielectric layer and an upper electrode layer are sequentially formed on the plurality of lower electrodes.

Abstract translation: 目的：提供一种制造半导体器件的方法，以通过防止下电极的变形来提高集成度。 构成：制备具有支撑层（500）的半导体衬底。 模具层（400）布置在支撑层上。 多个孔穿过模具层和支撑层。 多个下电极（600）形成在多个孔中。 电介质层和上电极层依次形成在多个下电极上。

公开(公告)号：KR1020140055741A

公开(公告)日：2014-05-09

申请号：KR1020120122989

申请日：2012-11-01

Applicant: 삼성전자주식회사

Inventor： 김형수 ,  이진수 ,  권호준 ,  박동균 ,  이지승 ,  최영석

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10817 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/91

Abstract: A manufacturing method of a capacitor of a semiconductor device according to an embodiment of the present invention comprises forming a mold structure and a polysilicon pattern on a semiconductor substrate in order; forming lower electrode holes passing through the mold structure by using the polysilicon pattern as an etching mask; forming a protective film covering the polysilicon pattern; forming lower electrodes in the lower electrode holes with the protective film; exposing the upper sidewalls of the lower electrodes by removing the polysilicon pattern and the protective film; exposing the lower sidewalls of the lower electrodes by removing the mold structure; and forming a dielectric film covering the surface of the lower electrodes and an upper electrode in order.

Abstract translation: 根据本发明的实施例的半导体器件的电容器的制造方法包括在半导体衬底上依次形成模具结构和多晶硅图案; 通过使用多晶硅图案作为蚀刻掩模形成穿过模具结构的下电极孔; 形成覆盖多晶硅图案的保护膜; 用保护膜在下电极孔中形成下电极; 通过去除多晶硅图案和保护膜来暴露下电极的上侧壁; 通过移除模具结构暴露下部电极的下侧壁; 以及依次形成覆盖下电极表面和上电极的电介质膜。