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    하이브리드 구조의 커패시터를 갖는 반도체 소자 및 그 제조방법
    4.
    发明公开
    하이브리드 구조의 커패시터를 갖는 반도체 소자 및 그 제조방법 审中-实审
    具有混合电容器的半导体器件及其制造方法

    公开(公告)号：KR1020140051688A

    公开(公告)日：2014-05-02

    申请号：KR1020120118020

    申请日：2012-10-23

    Applicant: 삼성전자주식회사

    Inventor： 박동균 ,  김한영 ,  김준 ,  박현 ,  오정환 ,  조민희

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L28/91 ,  H01L21/28562 ,  H01L21/31116 ,  H01L27/10852

    Abstract: The present invention relates to a semiconductor device and a method for fabricating the same. The present invention includes a lower electrode and an upper electrode which face each other between dielectric layers, capacitors arranged on a substrate, and a support pattern which touches the sidewalls of the lower electrodes and doubly supports the capacitors in an upper and a lower position. The lower electrode may include a first sub electrode of a pillar type electrically connected to a substrate and a second sub electrode of a cylinder type stacked on the first lower electrode. The support pattern may include an upper pattern touching the sidewalls of the upper part of the lower electrodes and a lower pattern which is vertically separated from the upper pattern, touches the lower sidewalls under the upper part of the lower electrodes, and is transferred with the plane shape of the upper pattern.

    Abstract translation: 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 本发明包括在电介质层之间彼此面对的下电极和上电极，布置在基板上的电容器和与下电极的侧壁接触并且在上下位置双重支撑电容器的支撑图案。 下部电极可以包括电连接到基板的柱状的第一子电极和层叠在第一下部电极上的圆筒状的第二子电极。 支撑图案可以包括接触下部电极的上部的侧壁的上部图案和与上部图案垂直分离的下部图案，与下部电极的上部下面的下侧壁接触，并且与 平面形状的上部图案。

    반도체 소자의 제조 방법
    5.
    发明公开
    반도체 소자의 제조 방법 有权
    制造半导体器件的方法

    公开(公告)号：KR1020130067136A

    公开(公告)日：2013-06-21

    申请号：KR1020110134000

    申请日：2011-12-13

    Applicant: 삼성전자주식회사

    Inventor： 최재형 ,  박기연 ,  김준 ,  유차영 ,  김윤수 ,  권호준 ,  강상열

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L28/60 ,  H01L28/92

    Abstract: PURPOSE: A method of manufacturing a semiconductor device is provided to improve the degree of integration by preventing the deformation of a lower electrode. CONSTITUTION: A semiconductor substrate with a support layer(500) is prepared. A mold layer(400) is arranged on the support layer. A plurality of holes pass through the mold layer and the support layer. A plurality of lower electrodes(600) are formed in the plurality of holes. A dielectric layer and an upper electrode layer are sequentially formed on the plurality of lower electrodes.

    Abstract translation: 目的：提供一种制造半导体器件的方法，以通过防止下电极的变形来提高集成度。 构成：制备具有支撑层（500）的半导体衬底。 模具层（400）布置在支撑层上。 多个孔穿过模具层和支撑层。 多个下电极（600）形成在多个孔中。 电介质层和上电极层依次形成在多个下电极上。

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