公开(公告)号：KR1020060123874A

公开(公告)日：2006-12-05

申请号：KR1020050045505

申请日：2005-05-30

Applicant: 삼성전자주식회사

Inventor： 이영욱 ,  기로트라쿠날사티압후산 ,  양성훈 ,  김병준 ,  김성진

IPC: G02F1/136

CPC classification number: G02F1/1368 ,  H01L27/127 ,  H01L29/78696

Abstract: A thin film transistor substrate is provided to adopt a depletion type transistor, thereby realizing a display device having high mobility and high on-current, by performing a low doping process in a semiconductor layer of the transistor. A first electrode(124) is formed on a substrate(110). An insulating layer is formed on the first electrode. A semiconductor layer(154) is formed on the insulating layer, and formed of an amorphous silicon material. A second electrode(173) and a third electrode(175) are formed on portions of the semiconductor layer, and separated from each other. A pixel electrode(191) is connected to the third electrode. A portion of the semiconductor layer, which is disposed between the second electrode and the third electrode, is doped with impurities.

Abstract translation: 提供薄膜晶体管基板以采用耗尽型晶体管，从而通过在晶体管的半导体层中执行低掺杂工艺来实现具有高迁移率和高导通电流的显示装置。 第一电极（124）形成在基板（110）上。 在第一电极上形成绝缘层。 半导体层（154）形成在绝缘层上，由非晶硅材料形成。 第二电极（173）和第三电极（175）形成在半导体层的部分上并彼此分离。 像素电极（191）连接到第三电极。 设置在第二电极和第三电极之间的半导体层的一部分掺杂有杂质。

公开(公告)号：KR1020060067334A

公开(公告)日：2006-06-20

申请号：KR1020040106076

申请日：2004-12-15

Applicant: 삼성전자주식회사

Inventor： 허종무 ,  양성훈 ,  기로트라쿠날사티압후산 ,  김병준

IPC: G02F1/136

CPC classification number: H01L27/124 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/1288

Abstract: 본 발명은, 기판 위에 도전층을 형성하는 단계, 상기 도전층 위에 포토레지스트 패턴을 형성하는 단계, 상기 포토레지스트 패턴에 따라 상기 도전층을 1차 식각하는 단계, 상기 포토레지스트 패턴을 제거하는 단계 및 상기 도전층을 2차 식각하는 단계를 포함하는 표시 장치용 배선의 형성 방법, 및 배선을 포함하는 박막 트랜지스터 표시판의 제조 방법을 제공한다.
배선, 식각, 프로파일, 돌기

公开(公告)号：KR1020080054583A

公开(公告)日：2008-06-18

申请号：KR1020060127002

申请日：2006-12-13

Applicant: 삼성전자주식회사

Inventor： 오화열 ,  이창호 ,  김병준 ,  양성훈 ,  최재호 ,  최용모 ,  기로트라쿠날사티압후산

IPC: H01L29/786

CPC classification number: H01L29/66765 ,  H01L29/458 ,  H01L29/78669

Abstract: A method for manufacturing a thin film transistor array panel is provided to enhance reliability by improving stability and mobility of a thin film transistor. A gate line is formed on a substrate(110). A gate insulating layer is formed on the gate line. An amorphous silicon layer having a thickness of 1500-1800 angstrom is formed on the gate insulating layer. An impure amorphous silicon layer having a thickness of 300-500 angstrom is formed on the amorphous silicon layer. An intrinsic semiconductor and an impure semiconductor are formed by etching the amorphous silicon layer and the impure amorphous silicon layer. A data line and a drain electrode(175) are formed on the impure semiconductor. A pixel electrode(191) is connected to the drain electrode.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，通过提高薄膜晶体管的稳定性和迁移率来提高可靠性。 在基板（110）上形成栅极线。 在栅极线上形成栅极绝缘层。 在栅极绝缘层上形成厚度为1500-1800埃的非晶硅层。 在非晶硅层上形成厚度为300-500埃的不纯的非晶硅层。 通过蚀刻非晶硅层和不纯的非晶硅层来形成本征半导体和不纯的半导体。 在不纯的半导体上形成数据线和漏电极（175）。 像素电极（191）连接到漏电极。

公开(公告)号：KR1020060112829A

公开(公告)日：2006-11-02

申请号：KR1020050035484

申请日：2005-04-28

Applicant: 삼성전자주식회사

Inventor： 김병준 ,  황보상우 ,  기로트라쿠날사티압후산 ,  양성훈

IPC: H01L29/786

CPC classification number: H01L29/78696 ,  H01L21/2053 ,  H01L29/66765 ,  H01L29/78678

Abstract: A thin film transistor is provided to prevent an electrical characteristic of a thin film transistor from being deteriorated while a gate insulation layer is not damaged by varying a mixture ratio of reaction gas when a semiconductor is formed by a CVD method. A first electrode is formed on a substrate. A gate insulation layer is formed on the first electrode. A semiconductor(151) overlaps the first electrode over the gate insulation layer, composed of first and second silicon layers having different densities. At least a part of first and second electrodes overlaps the semiconductor. A resistive contact member is formed between first and second electrodes and the semiconductor.

Abstract translation: 提供了一种薄膜晶体管，以防止薄膜晶体管的电特性劣化，而当通过CVD法形成半导体时，通过改变反应气体的混合比没有损坏栅极绝缘层。 在基板上形成第一电极。 在第一电极上形成栅极绝缘层。 半导体（151）在栅极绝缘层上的第一电极重叠，由具有不同密度的第一和第二硅层组成。 第一和第二电极的至少一部分与半导体重叠。 在第一和第二电极和半导体之间形成电阻接触构件。