公开(公告)号：KR1020080076447A

公开(公告)日：2008-08-20

申请号：KR1020070016375

申请日：2007-02-16

Applicant: 삼성전자주식회사

Inventor： 오화열 ,  양성훈 ,  최재호 ,  김병준 ,  김성렬 ,  최용모

IPC: H01L29/786

CPC classification number: H01L29/66765 ,  H01L21/02271 ,  H01L21/0262 ,  H01L21/2053 ,  H01L29/4908 ,  H01L29/78603

Abstract: A method for manufacturing a thin film transistor substrate is provided to prevent on current of the thin film transistor formed through a lower temperature process from lowering by adjusting a mixing rate of gas to improve a gate insulation layer and a semiconductor layer. A method for manufacturing a thin film transistor substrate includes the steps of: forming a gate electrode(120) on a substrate(110); forming a gate insulation layer(130) on the substrate with the gate electrode by using gas containing H2 and SiH4 which are mixed at the rate of 18:1~22:1 and gas containing N2 and NH3 which are mixed at the rate of 8:1~12:1 at 200 °C~250 °C; forming a semiconductor layer(142) on the substrate with the gate insulation layer by using gas containing H2 and SiH4 which are mixed at the rate of 13:1~17:1 at 200 °C~250 °C; forming an ohmic contact layer(144) on the semiconductor layer at 200 °C~250 °C; forming source and drain electrodes(152,154) on the ohmic layer which are separated from each other, with having a channel forming region of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管基板的方法，以通过调节气体的混合速率以改善栅极绝缘层和半导体层来防止通过较低温度工艺形成的薄膜晶体管的导通电流降低。 制造薄膜晶体管基板的方法包括以下步骤：在基板（110）上形成栅电极（120）; 通过使用以18：1〜22：1的速度混合的含有H2和SiH4的气体和以N2的比例混合的N 2和NH 3的气体，在栅电极的基板上形成栅极绝缘层（130） ：200〜250℃1〜12：1; 通过使用含有H2和SiH4的气体在200℃〜250℃下以13：1〜17：1的比例混合，在栅极绝缘层上形成半导体层（142）; 在200℃〜250℃在半导体层上形成欧姆接触层（144）; 在所述欧姆层上形成具有所述半导体层的沟道形成区域的彼此分离的源极和漏极（152,154）。

公开(公告)号：KR1020080054927A

公开(公告)日：2008-06-19

申请号：KR1020060127606

申请日：2006-12-14

Applicant: 삼성전자주식회사

Inventor： 최용모 ,  김병준 ,  양성훈 ,  허종무 ,  오화열 ,  최재호

IPC: H05B33/02

CPC classification number: H01L27/1285 ,  H01L27/1222 ,  H01L51/56

Abstract: A manufacturing method of an organic light emitting diode display is provided to improve Ion and Ioff characteristics of a thin film transistor through plasma treatment. A manufacturing method of an organic light emitting diode display includes the steps of: forming a gate line including a first control electrode(124a) and a second control electrode(124b) on a substrate; forming a gate insulating layer on the gate line and the second control electrode; forming an amorphous silicon layer on the gate insulating layer; forming a polycrystalline silicon layer by annealing the amorphous silicon layer; performing H2 plasma treatment on the polycrystalline silicon layer; forming first and second semiconductors(154a,154b) by patterning the polycrystalline silicon layer; forming a data line(171) having a first input electrode(173a), a driving voltage line(172) having a second input electrode(173b), and first and second output electrodes(175a,175b) on the first and second semiconductors; forming a passivation layer on the data line, the driving voltage line, and the first and second output electrodes; forming a connecting member(85) to connect the first output electrode and the second input electrode and a first electrode(191) connected to the second output electrode on the passivation layer; forming a partition including an opening on the first electrode; forming a light emitting member on the opening; and forming a second electrode on the light emitting member.

Abstract translation: 提供了一种有机发光二极管显示器的制造方法，以通过等离子体处理改善薄膜晶体管的离子和离子化特性。 有机发光二极管显示器的制造方法包括以下步骤：在基板上形成包括第一控制电极（124a）和第二控制电极（124b）的栅极线; 在栅极线和第二控制电极上形成栅极绝缘层; 在所述栅绝缘层上形成非晶硅层; 通过退火所述非晶硅层形成多晶硅层; 在多晶硅层上进行H2等离子体处理; 通过构图多晶硅层形成第一和第二半导体（154a，154b）; 形成具有第一输入电极（173a）的数据线（171），具有第二输入电极（173b）的驱动电压线（172）和第一和第二半导体上的第一和第二输出电极（175a，175b） 在数据线，驱动电压线以及第一和第二输出电极上形成钝化层; 形成用于连接第一输出电极和第二输入电极的连接部件（85）和与钝化层上的第二输出电极连接的第一电极（191）; 在所述第一电极上形成包括开口的隔板; 在所述开口上形成发光部件; 以及在所述发光部件上形成第二电极。

公开(公告)号：KR1020060133827A

公开(公告)日：2006-12-27

申请号：KR1020050053678

申请日：2005-06-21

Applicant: 삼성전자주식회사

Inventor： 오화열

IPC: G02F1/136

CPC classification number: H01L27/1244 ,  G02F1/1368 ,  H01L27/1259

Abstract: A method for manufacturing a thin film transistor substrate is provided to minimize the protrusions of an ohmic contact pattern and a semiconductor pattern, thereby improving the aperture ratio, by substantially aligning the lateral portions of the ohmic contact pattern and the semiconductor pattern with the end of an upper conductive layer. A gate insulating layer(30), a semiconductor layer, an ohmic contact layer, and a conductive layer are sequentially deposited on a substrate having a gate wire. A photoresist pattern(112) is formed on the conductive layer. The conductive layer is pattern-etched to expose the ohmic contact layer using the photoresist pattern. The ohmic contact layer and the semiconductor layer are pattern-etched to form an ohmic contact pattern(54) and a semiconductor pattern(44) using the photoresist pattern. The photoresist pattern is downsized to expose the lateral portions of the ohmic contact pattern and the semiconductor pattern. The lateral portions of the ohmic contact pattern and the semiconductor pattern are etched, thereby substantially aligning the outside profiles of the ohmic contact pattern and the semiconductor pattern with the outside profile of the patterned conductive layer(64). The patterned conductive layer and ohmic contact pattern are pattern-etched to expose a channel portion of the semiconductor pattern.

Abstract translation: 提供了一种用于制造薄膜晶体管基板的方法，以使欧姆接触图案和半导体图案的突起最小化，从而通过使欧姆接触图案和半导体图案的横向部分与 上导电层。 栅极绝缘层（30），半导体层，欧姆接触层和导电层依次沉积在具有栅极线的基板上。 在导电层上形成光致抗蚀剂图案（112）。 使用光致抗蚀剂图案对导电层进行图案蚀刻以暴露欧姆接触层。 欧姆接触层和半导体层被图案蚀刻以形成使用光致抗蚀剂图案的欧姆接触图案（54）和半导体图案（44）。 光致抗蚀剂图案被小型化以暴露欧姆接触图案和半导体图案的横向部分。 蚀刻欧姆接触图案和半导体图形的横向部分，从而将欧姆接触图案和半导体图案的外部轮廓基本上对准图案化导电层（64）的外部轮廓。 图案化导电层和欧姆接触图案被图案蚀刻以暴露半导体图案的沟道部分。

公开(公告)号：KR1020080036281A

公开(公告)日：2008-04-28

申请号：KR1020060102707

申请日：2006-10-23

Applicant: 삼성전자주식회사

Inventor： 최재호 ,  양성훈 ,  김병준 ,  오화열 ,  최용모

IPC: G02F1/136

CPC classification number: G02F1/1362 ,  G02F2001/133302 ,  H01L27/1214

Abstract: A method for manufacturing a TFT(Thin Film Transistor) substrate is provided to optimize plasma power or a gas type when performing the plasma processing of the channel area of a TFT in the manufacture of a TFT substrate using soda lime glass, thereby preventing the deterioration of the TFT and improving driving characteristics. A method for manufacturing a TFT substrate comprises the following steps of: forming gate wiring including a gate line(122) and a gate electrode(124) on a substrate(110); forming a gate insulating film(130) on the substrate on which the gate wiring is formed; forming data wiring including an active layer(140), a data line(152), a source electrode(154), and a drain electrode on the gate insulating layer; performing the plasma processing of the channel area of the active layer with a range of 500W to 1000W; forming a protection layer(170) at temperature below 250 degrees Celsius on the substrate on which the active layer and the data wiring are formed; and forming a pixel electrode(180) which is electrically connected to the drain electrode on the protection layer.

Abstract translation: 提供了一种用于制造TFT（薄膜晶体管）基板的方法，以在使用钠钙玻璃制造TFT基板时执行TFT的沟道区域的等离子体处理来优化等离子体功率或气体类型，从而防止劣化 并改善驱动特性。 一种制造TFT基板的方法包括以下步骤：在基板（110）上形成包括栅极线（122）和栅电极（124）的栅极布线; 在其上形成有栅极布线的基板上形成栅极绝缘膜（130）; 在所述栅极绝缘层上形成包括有源层（140），数据线（152），源电极（154）和漏电极的数据布线; 以500W〜1000W的范围进行有源层的沟道区域的等离子体处理; 在其上形成有源层和数据布线的基板上形成温度低于250摄氏度的保护层（170）; 以及形成与保护层上的漏电极电连接的像素电极（180）。

公开(公告)号：KR1020080004005A

公开(公告)日：2008-01-09

申请号：KR1020060062424

申请日：2006-07-04

Applicant: 삼성전자주식회사

Inventor： 이영욱 ,  이우근 ,  오화열 ,  차연희 ,  박정인

IPC: G02F1/136

CPC classification number: G02F1/136 ,  G03F1/144 ,  H01L27/124 ,  H01L29/786 ,  H01L51/56

Abstract: A method of fabricating a thin film transistor substrate is provided to reduce a channel length between a source electrode and a drain electrode of a thin film transistor through a single slit mask having a notch. A gate pattern including a gate line and a gate electrode(20) is formed. A gate insulating layer(30), an active layer(40), an ohmic-contact layer(45) and a data metal layer are formed on the gate pattern. A channel of a thin film transistor and a data pattern including a source electrode(60), a drain electrode(70) and a data line(50) are formed at the data metal layer by using a single slit mask including a notch. A passivation layer and a pixel electrode(100) connected with the drain electrode are formed on the data pattern. The forming of the channel of the thin film transistor and the data pattern includes forming photoresist on the data metal layer, exposing the photoresist by using the single slit mask, and etching the data metal layer without a patterned photoresist pattern.

Abstract translation: 提供一种制造薄膜晶体管衬底的方法，通过具有缺口的单个狭缝掩模来减小薄膜晶体管的源电极和漏电极之间的沟道长度。 形成包括栅极线和栅电极（20）的栅极图案。 在栅极图案上形成栅绝缘层（30），有源层（40），欧姆接触层（45）和数据金属层。 通过使用包括凹口的单个狭缝掩模，在数据金属层上形成薄膜晶体管的沟道和包括源极（60），漏极（70）和数据线（50）的数据图案。 在数据图形上形成钝化层和与漏电极连接的像素电极（100）。 薄膜晶体管的通道的形成和数据图形包括在数据金属层上形成光致抗蚀剂，通过使用单个狭缝掩模曝光光致抗蚀剂，并且在没有图案化的光致抗蚀剂图案的情况下蚀刻数据金属层。

公开(公告)号：KR1020070049771A

公开(公告)日：2007-05-14

申请号：KR1020050106910

申请日：2005-11-09

Applicant: 삼성전자주식회사

Inventor： 오화열

IPC: G02F1/13 ,  G02F1/1345

CPC classification number: G02F1/1345 ,  G02F1/1309 ,  G02F2001/133354 ,  G02F2202/99

Abstract: 본 발명은 액정표시장치 및 그 제조방법을 제공한다. 본 발명의 액정표시장치는 다층 패턴을 형성함에 있어 상층과 하층의 패턴간 오정렬 여부를 검사하는 정렬 검사 패턴을 포함한다. 상기 정렬 검사 패턴은 평면부의 외곽선이 원형의 형상을 가지며, 이를 이용하면 상층과 하층의 패턴간의 오정렬시 오정렬 각도가 이탈 거리 등이 용이하게 파악되는 장점이 있다.
또한 본 발명의 액정표시장치의 제조방법에 의하면, 상층의 패턴을 위한 포토레지스트의 식각 마스크 형성시 포토레지스트 정렬 검사 패턴이 동시에 형성되며, 이를 이용하면 하층에 형성된 패턴과 상층에 형성될 패턴간의 오정렬 여부가 미리 확인될 수 있다.
액정, 패턴, 정렬,

公开(公告)号：KR1020080064342A

公开(公告)日：2008-07-09

申请号：KR1020070001134

申请日：2007-01-04

Applicant: 삼성전자주식회사

Inventor： 양성훈 ,  김병준 ,  정수임 ,  오화열 ,  최재호 ,  기로트라쿠날

IPC: H01L29/786

CPC classification number: G02F1/1368 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66765

Abstract: A method for manufacturing a thin film transistor display panel is provided to realize dark black during driving of a black screen by removing particles generated on a surface of a first gate insulation layer. A method for manufacturing a thin film transistor display panel includes: forming a gate wire(22) having a gate electrode(26) on an insulation substrate; forming a first gate insulation layer covering the gate wire, carrying out first plasma processing on a surface of the first gate insulation layer; washing a surface of the first gate insulation layer; carrying second plasma processing on a surface of the first gate insulation layer; forming a second gate insulation layer on the first gate insulation layer; forming a semiconductor pattern on a second gate insulation layer; forming a data wire including source and drain electrodes that are separated from each other on the semiconductor pattern; and forming a pixel electrode electrically connected to the drain electrode.

Abstract translation: 提供一种制造薄膜晶体管显示面板的方法，通过去除在第一栅极绝缘层的表面上产生的颗粒来在黑色屏幕的驱动期间实现暗黑色。 一种制造薄膜晶体管显示面板的方法包括：在绝缘基板上形成具有栅电极（26）的栅极线（22）; 形成覆盖所述栅极线的第一栅极绝缘层，在所述第一栅极绝缘层的表面上进行第一等离子体处理; 洗涤第一栅极绝缘层的表面; 在第一栅极绝缘层的表面上承载第二等离子体处理; 在所述第一栅极绝缘层上形成第二栅极绝缘层; 在第二栅极绝缘层上形成半导体图案; 形成包括在所述半导体图案上彼此分离的源极和漏极的数据线; 以及形成与漏电极电连接的像素电极。

公开(公告)号：KR1020080054583A

公开(公告)日：2008-06-18

申请号：KR1020060127002

申请日：2006-12-13

Applicant: 삼성전자주식회사

Inventor： 오화열 ,  이창호 ,  김병준 ,  양성훈 ,  최재호 ,  최용모 ,  기로트라쿠날사티압후산

IPC: H01L29/786

CPC classification number: H01L29/66765 ,  H01L29/458 ,  H01L29/78669

Abstract: A method for manufacturing a thin film transistor array panel is provided to enhance reliability by improving stability and mobility of a thin film transistor. A gate line is formed on a substrate(110). A gate insulating layer is formed on the gate line. An amorphous silicon layer having a thickness of 1500-1800 angstrom is formed on the gate insulating layer. An impure amorphous silicon layer having a thickness of 300-500 angstrom is formed on the amorphous silicon layer. An intrinsic semiconductor and an impure semiconductor are formed by etching the amorphous silicon layer and the impure amorphous silicon layer. A data line and a drain electrode(175) are formed on the impure semiconductor. A pixel electrode(191) is connected to the drain electrode.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，通过提高薄膜晶体管的稳定性和迁移率来提高可靠性。 在基板（110）上形成栅极线。 在栅极线上形成栅极绝缘层。 在栅极绝缘层上形成厚度为1500-1800埃的非晶硅层。 在非晶硅层上形成厚度为300-500埃的不纯的非晶硅层。 通过蚀刻非晶硅层和不纯的非晶硅层来形成本征半导体和不纯的半导体。 在不纯的半导体上形成数据线和漏电极（175）。 像素电极（191）连接到漏电极。

公开(公告)号：KR1020080021215A

公开(公告)日：2008-03-07

申请号：KR1020060083076

申请日：2006-08-30

Applicant: 삼성전자주식회사

Inventor： 오화열 ,  김병준 ,  양성훈 ,  강민 ,  최재호 ,  최용모 ,  손경근

IPC: G02F1/1335

CPC classification number: G02F1/133509 ,  G02F1/1362 ,  G02F2001/133397

Abstract: A thin film transistor substrate and a method of manufacturing the thin film transistor substrate are provided to form a black matrix and a color filter pattern on the backside of a thin film transistor substrate to remove image sticking caused by ionic impurities according to the material of the color filter pattern and the black matrix and image sticking caused by light leakage current generated from an active layer. A thin film transistor substrate includes a plurality of gate lines, a plurality of data lines(62), a plurality of thin film transistors, a plurality of pixel electrodes(82), a black matrix(91), and red, green and blue color filters(92R,92G,92B). The gate lines are formed on one side of an insulating substrate and extended in a first direction. The data lines are extended in a second direction and intersect the gate lines. The thin film transistors are respectively connected to the gate lines and the data lines. The pixel electrodes are respectively connected to the thin film transistors. The black matrix is formed on the other side of the insulating substrate and superposed on the gate lines, the data lines and the thin film transistors. The color filters are formed on the other side of the insulating layer and superposed on the pixel electrodes.

Abstract translation: 提供薄膜晶体管基板和制造薄膜晶体管基板的方法，以在薄膜晶体管基板的背面上形成黑色矩阵和滤色器图案，以根据材料制造由离子杂质引起的图像残留 滤色器图案以及由活性层产生的漏光电流引起的黑色矩阵和图像残留。 薄膜晶体管基板包括多个栅极线，多个数据线（62），多个薄膜晶体管，多个像素电极（82），黑矩阵（91）以及红，绿和蓝 滤色片（92R，92G，92B）。 栅极线形成在绝缘基板的一侧并沿第一方向延伸。 数据线在第二方向上延伸并与栅极线相交。 薄膜晶体管分别连接到栅极线和数据线。 像素电极分别连接到薄膜晶体管。 黑矩阵形成在绝缘基板的另一侧，并叠加在栅极线，数据线和薄膜晶体管上。 滤色器形成在绝缘层的另一侧并且叠置在像素电极上。

公开(公告)号：KR1020080105322A

公开(公告)日：2008-12-04

申请号：KR1020070052761

申请日：2007-05-30

Applicant: 삼성전자주식회사

Inventor： 최재호 ,  김병준 ,  양성훈 ,  이창호 ,  김성렬 ,  오화열 ,  최용모

IPC: G02F1/136

CPC classification number: G02F1/136286 ,  G02F1/13458 ,  G02F1/1368 ,  H01L27/1214 ,  H01L29/4908

Abstract: A method for manufacturing TFT substrate, and a method for manufacturing an LCD panel using the same are provided to improve the production yield and display characteristics. Gate wiring parts(121,GL,CL,SE1) include a gate line(GL) in the top of the substrate and gate electrode(121). A step for processing with plasma for 1 20 second or 120 second The surface of the gate wiring part is processed with plasma for 20 seconds to 120 seconds for removing the oxide layer on the gate wiring part. A gate insulating layer which covers the gate wiring part is formed on the substrate. The data line, source electrode(124), and a drain electrode(125) are formed on the gate isolation layer.

Abstract translation: 提供TFT基板的制造方法以及使用该TFT基板的液晶显示面板的制造方法，以提高成品率和显示特性。 栅极配线部（121，GL，CL，SE1）在基板的顶部和栅电极（121）中包括栅极线（GL）。 用等离子体处理1 20秒或120秒的步骤用等离子体处理20分钟至120秒的栅极布线部分的表面，以去除栅极布线部分上的氧化物层。 在基板上形成覆盖栅极布线部的栅极绝缘层。 数据线，源极（124）和漏电极（125）形成在栅极隔离层上。