公开(公告)号：KR101695846B1

公开(公告)日：2017-01-16

申请号：KR1020100018644

申请日：2010-03-02

Applicant: 삼성전자주식회사

Inventor： 임충빈 ,  목승곤 ,  박진우 ,  최대영 ,  김미연

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012

Abstract: 적층형반도체패키지및 그제조방법을제공한다. 제 1 인쇄회로기판과상기제 1 인쇄회로기판에실장되는제 1 반도체소자를구비하는제 1 반도체패키지와, 상기제 1 반도체패키지에적층되고, 제 2 인쇄회로기판과상기제 2 인쇄회로기판에실장되는제 2 반도체소자를구비하는제 2 반도체패키지를제공한다. 상기제 1 반도체소자를관통하여상기제 2 반도체패키지와상기제 1 인쇄회로기판을전기적으로연결하는적어도하나의제 1 관통전극을제공한다.

Abstract translation: 半导体封装包括第一半导体封装，包括第一印刷电路板和安装在第一印刷电路板上的第一半导体器件，以及堆叠在第一半导体封装上的第二半导体封装，并且包括第二印刷电路板和第二半导体 装置安装在第二印刷电路板上。 半导体封装包括至少一个第一通孔，其通过第一半导体器件将第二半导体封装电连接到第一印刷电路板。

公开(公告)号：KR1020120089150A

公开(公告)日：2012-08-09

申请号：KR1020110010347

申请日：2011-02-01

Applicant: 삼성전자주식회사

Inventor： 홍지선 ,  최대영 ,  김미연

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PURPOSE: A package on package is provided to improve lamination yield by preventing short circuit between connecting members. CONSTITUTION: A second semiconductor package(200) includes a second substrate(210), a second semiconductor chip(220) and a second connecting member. A connecting part(260) is formed by combining a first connecting member and the second connecting member. The connecting part connects a first semiconductor package and the second semiconductor package. The connecting part includes a core and a fusing conductive layer. The fusing conductive layer is contacted to the lower part of the second substrate and the upper part of a first substrate.

Abstract translation: 目的：提供包装封装，以通过防止连接构件之间的短路来提高层压率。 构成：第二半导体封装（200）包括第二衬底（210），第二半导体芯片（220）和第二连接构件。 通过组合第一连接构件和第二连接构件形成连接部分（260）。 连接部分连接第一半导体封装和第二半导体封装。 连接部分包括芯和熔化导电层。 熔融导电层与第二基板的下部和第一基板的上部接触。

公开(公告)号：KR1020120061492A

公开(公告)日：2012-06-13

申请号：KR1020100122826

申请日：2010-12-03

Applicant: 삼성전자주식회사

Inventor： 김철우 ,  김미연 ,  민태홍 ,  김동한

IPC: H01L21/60 ,  H01L23/48 ,  H01L23/12

CPC classification number: H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: PURPOSE: A semiconductor package, a substrate for the same, a circuit board system, a semiconductor module, an electronic system, and formation methods thereof are provided to improve an integration degree of a semiconductor chip by reducing an interval and a pitch between input/output pads. CONSTITUTION: A bare substrate includes a bump land(111) which is exposed on one side of the bare substrate. A bump adhesion part(147) is formed on the exposed bump land. A metal post(157) is electrically connected to the bump land. A chip pad is exposed on one side of a semiconductor chip. The metal post and the chip pad are electrically connected to each other.

Abstract translation: 目的：提供半导体封装，其基板，电路板系统，半导体模块，电子系统及其形成方法，以通过减小半导体芯片的间隔和间距来提高半导体芯片的集成度， 输出板。 构成：裸衬底包括暴露在裸衬底一侧的凹凸面（111）。 在露出的隆起焊盘上形成凸块粘附部件（147）。 金属柱（157）电连接到凸起焊盘。 芯片焊盘暴露在半导体芯片的一侧。 金属柱和芯片焊盘彼此电连接。

公开(公告)号：KR1020110008831A

公开(公告)日：2011-01-27

申请号：KR1020090066364

申请日：2009-07-21

Applicant: 삼성전자주식회사

Inventor： 이진호 ,  임충빈 ,  박진우 ,  최대영 ,  김미연

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PURPOSE: A semiconductor package and a method of fabricating the same are provided to reduce the thickness of a whole package by inserting a second sub-package into the recess part of a first sub-package. CONSTITUTION: A base substrate comprises a first side and a second side which are opposite to each other. A recess part is formed in a second side. A first semiconductor chip(20) is mounted in a first side. A first ball land(16) is arranged in a second side excluding the recess part. A second semiconductor chip comprises a penetration via which is electrically connected to a connection pad. A second ball land is electrically connected to the penetration via.

Abstract translation: 目的：提供半导体封装及其制造方法，以通过将第二子封装插入第一子封装的凹部来减小整个封装的厚度。 构成：基底基板包括彼此相对的第一侧和第二侧。 在第二侧形成凹部。 第一半导体芯片（20）安装在第一侧。 第一球面（16）布置在除了凹部以外的第二侧。 第二半导体芯片包括电连接到连接焊盘的穿透孔。 第二个球场电连接到穿透通孔。

公开(公告)号：KR1020080004747A

公开(公告)日：2008-01-10

申请号：KR1020060063420

申请日：2006-07-06

Applicant: 삼성전자주식회사

Inventor： 김미연 ,  유지용

IPC: H01L21/027

CPC classification number: G03F7/2022 ,  G03F7/70058 ,  G03F7/70216 ,  G03F7/70716 ,  G03F7/70741

Abstract: An apparatus for exposing a semiconductor substrate is provided to suppress a lifting phenomenon of a dummy pattern formed in an edge region of the substrate to reduce a step of a chip-in pattern and improve uniformity. An apparatus(100) for exposing a semiconductor substrate(W) includes an illumination unit(102), a library(126), a reticle stage(118), a projection unit(122), and a substrate stage(124). The illumination unit provides illumination light. The library is installed adjacent to the illumination unit. The library houses reticles(114) for forming a dummy pattern(116) having a region where a mesh-type pattern is formed for exposing regions being in contact with an edge of the substrate. The reticle stage supports the reticle selected from the library. The projection unit induces projection light passing the reticle to the substrate. The substrate stage supports the substrate.

Abstract translation: 提供一种用于暴露半导体衬底的装置，以抑制形成在衬底的边缘区域中的虚拟图案的提升现象，以减少芯片形成的步骤并提高均匀性。 用于曝光半导体衬底（W）的设备（100）包括照明单元（102），库（126），标线片平台（118），投影单元（122）和衬底台（124）。 照明单元提供照明光。 图书馆安装在照明装置附近。 图书馆设有用于形成具有形成网状图案的区域的虚拟图案（116）的掩模版（114），用于暴露与基板边缘接触的区域。 标线台支持从图书馆中选出的掩模版。 投影单元将投射光通过掩模版到基板。 衬底台支撑衬底。

公开(公告)号：KR101767381B1

公开(公告)日：2017-08-11

申请号：KR1020100139485

申请日：2010-12-30

Applicant: 삼성전자주식회사

Inventor： 김현기 ,  최대영 ,  김미연

IPC: H01L23/498 ,  H05K3/46

CPC classification number: H05K3/4602 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/15311 ,  H05K3/4608 ,  H05K2201/068 ,  H05K2201/09136 ,  H01L2924/00

Abstract: 인쇄회로기판및 이를포함하는반도체패키지가제공된다. 인쇄회로기판은서로다른물질로형성된복수의층이적층된구조를포함하는코어층; 상기코어층상부에배치된상부배선층; 및상기코어층하부에배치된하부배선층을포함한다.

Abstract translation: 提供印刷电路板和包括该印刷电路板的半导体封装。 1。一种印刷电路板，包括：芯层，所述芯层包括其中堆叠由不同材料形成的多个层的结构; 布置在芯层上的上布线层; 以及布置在芯层下面的下布线层。

公开(公告)号：KR1020110107180A

公开(公告)日：2011-09-30

申请号：KR1020100026393

申请日：2010-03-24

Applicant: 삼성전자주식회사

Inventor： 김태훈 ,  박진우 ,  최대영 ,  김미연 ,  이선혜

IPC: H01L23/522 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/14 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00012

Abstract: 패키지-온-패키지 형성방법을 제공한다. 웨이퍼 레벨 몰딩(wafer level molding) 공정을 이용하여 웨이퍼를 덮는 봉지재(encapsulant)를 형성한다. 상기 웨이퍼는 다수의 반도체 칩들 및 상기 반도체 칩들을 관통하는 다수의 관통 전극들(through silicon via; TSV)을 구비한다. 상기 봉지재는 상기 관통 전극들에 정렬된 개구부들을 갖는다. 상기 봉지재 및 상기 반도체 칩들을 분할하여 다수의 반도체 패키지들을 형성한다. 상기 반도체 패키지들 중 선택된 하나의 상부에 다른 반도체 패키지를 적층 한다. 상기 다른 반도체 패키지는 상기 관통 전극들에 전기적으로 접속된다.

公开(公告)号：KR1020050064344A

公开(公告)日：2005-06-29

申请号：KR1020030095703

申请日：2003-12-23

Applicant: 삼성전자주식회사

Inventor： 김대중 ,  심우석 ,  김미연

IPC: H01L21/027

Abstract: 웨이퍼 에지를 노광하는 시스템과 웨이퍼 에지 노광 방법을 제공한다. 기존의 노광 시스템에 광원에서 나오는 빔을 웨이퍼 전면으로 확장시키기 위한 빔 익스팬더와 웨이퍼 에지 부분만 노광하기 위한 에지 노광 마스크를 도입함으로써 웨이퍼 에지를 전면 노광한다. 웨이퍼 에지를 한번에 전면 노광함으로써 웨이퍼 에지 노광에 걸리는 시간을 단축할 수 있다.

公开(公告)号：KR1020110130017A

公开(公告)日：2011-12-05

申请号：KR1020100049422

申请日：2010-05-27

Applicant: 삼성전자주식회사

Inventor： 김상욱 ,  박진우 ,  최대영 ,  김미연 ,  이선혜

IPC: H01L23/12

CPC classification number: H01L23/147 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: PURPOSE: A multi-chip package and a manufacturing method thereof are provided to improve electrical connecting reliability between a first semiconductor package and a second semiconductor package by electrically interlinking first connecting terminals and second connecting terminals using an interposer chip as intermediation. CONSTITUTION: A multi-chip package comprises a first semiconductor package, a second semiconductor package(200), and an interposer chip(300). The second semiconductor package is arranged on the top of the first semiconductor package. The interposer chip is located between the first semiconductor package and the second semiconductor package. The interposer chip has an accommodating groove which accepts a first package. The interposer chip comprises an interposer board and an interposer terminal(320). The interposer terminal electrically interlinks the first semiconductor package and the second semiconductor package.

Abstract translation: 目的：提供一种多芯片封装及其制造方法，以通过使用内插器芯片进行电连接来连接第一连接端子和第二连接端子来提高第一半导体封装和第二半导体封装之间的电连接可靠性。 构成：多芯片封装包括第一半导体封装，第二半导体封装（200）和插入器芯片（300）。 第二半导体封装布置在第一半导体封装的顶部。 插入器芯片位于第一半导体封装和第二半导体封装之间。 插入片具有容纳第一封装的容纳槽。 插入器芯片包括插入器板和插入器端子（320）。 插入器端子电连接第一半导体封装和第二半导体封装。

公开(公告)号：KR1020110050231A

公开(公告)日：2011-05-13

申请号：KR1020090107119

申请日：2009-11-06

Applicant: 삼성전자주식회사

Inventor： 김상욱 ,  류효창 ,  박진우 ,  최대영 ,  김미연

IPC: H01L23/28

CPC classification number: H01L23/3128 ,  H01L23/16 ,  H01L23/562 ,  H01L24/13 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PURPOSE: A semiconductor package and a method of forming the same are provided to protect a semiconductor chip from thermal/physical stress due to a molding film by arranging a stress alleviation unit in a semiconductor chip before forming the molding film. CONSTITUTION: In a semiconductor package and a method of forming the same, a semiconductor chip(120) is attached to a substrate(100) through an adhesive. At least one stress alleviation unit(200) is arranged in one side of the semiconductor chip. The semiconductor chip includes a weak part. The stress alleviation unit is overlapped with the weak part. A molding film covers the side of the stress alleviation unit and at least part of the semiconductor chip.

Abstract translation: 目的：提供半导体封装及其形成方法，以在形成模制薄膜之前通过在半导体芯片中布置应力缓解单元来保护半导体芯片免受因模制薄膜造成的热/物理应力。 构成：在半导体封装及其形成方法中，通过粘合剂将半导体芯片（120）附接到基板（100）。 至少一个应力消除单元（200）布置在半导体芯片的一侧。 半导体芯片包括弱部分。 应力缓解单元与弱部重叠。 成型膜覆盖应力消除单元的一侧和半导体芯片的至少一部分。