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公开(公告)号：KR1020040077273A
公开(公告)日：2004-09-04
申请号：KR1020030012773
申请日：2003-02-28
Applicant: 삼성전자주식회사
Inventor： 김수한
IPC: H01L21/027
Abstract: PURPOSE: An apparatus for removing a photoresist from a semiconductor wafer and an operating method thereof are provided to prevent the contamination due to the photoresist by installing a photoresist removal device at a lateral part of an edge of a wafer. CONSTITUTION: A cleaning pad(110) is installed at one side of a semiconductor wafer. The cleaning pad is adhered to an arm(130). A cleaning solution supply unit(160) is adhered to the arm in order to supply a cleaning solution to the cleaning pad. The cleaning pad is formed with a predetermined material for absorbing the cleaning solution. In addition, the cleaning pad is formed with the predetermined material having the durability, the etching resistance for the cleaning solution, and the abrasion resistance for the surface of the wafer.
Abstract translation: 目的：提供一种用于从半导体晶片去除光致抗蚀剂的设备及其操作方法，以通过在晶片的边缘的侧部安装光致抗蚀剂去除装置来防止由光致抗蚀剂引起的污染。 构成：清洁垫（110）安装在半导体晶片的一侧。 清洁垫粘附到臂（130）上。 清洁溶液供应单元（160）粘附到臂上，以便将清洁溶液供应到清洁垫。 清洁垫由用于吸收清洁溶液的预定材料形成。 此外，清洁垫由具有耐久性，清洁溶液的耐蚀刻性和对于晶片表面的耐磨性的预定材料形成。
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公开(公告)号：KR1019940003223B1
公开(公告)日：1994-04-16
申请号：KR1019910017326
申请日：1991-10-02
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: Semiconductor device comprising a device isolating region by trenches having the same or different widths on a semiconductor substrate, wherein an active region which is located as an island-shape on the semiconductor substrate having a boundary line with the device isolation region comprises trenches formed with a predetermined width along the outer wall of said trench, planaized insulating layers formed on the inactive region of the substrate between trenches which wrap another active region, spacers formed by an insulating material which fills up trenches, thereby accomplishing a high density semiconductor device.
Abstract translation: 半导体器件包括在半导体衬底上具有相同或不同宽度的沟槽的器件隔离区域，其中位于具有与器件隔离区域的边界线的半导体衬底上的岛状的有源区域包括形成有沟道的沟槽， 沿着所述沟槽的外壁的预定宽度，在包围另一有源区的沟槽之间的基板的非活性区域上形成的平面化绝缘层，由填充沟槽的绝缘材料形成的间隔物，从而实现高密度半导体器件。
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公开(公告)号：KR101551449B1
公开(公告)日：2015-09-08
申请号：KR1020090015933
申请日：2009-02-25
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5642 , G11C16/26
Abstract: 본발명의실시예에따른비휘발성메모리장치는, 복수의워드라인들및 복수의비트라인들의교차영역에형성되는복수의메모리셀들을갖는셀 어레이, 어드레스에응답하여상기복수의워드라인들중 어느하나를선택하는어드레스디코더, 상기선택된워드라인에연결된메모리셀들에프로그램데이터를쓰기위한쓰기회로, 및쓰기동작시복수의밴드프로그램동작들이순차적으로수행되도록상기어드레스디코더및 쓰기회로를제어하는제어회로를포함하되, 상기제어회로는밴드프로그램동작시다음밴드프로그램의쓰기조건을선택할수 있다.
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公开(公告)号：KR1020100096863A
公开(公告)日：2010-09-02
申请号：KR1020090015933
申请日：2009-02-25
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5642 , G11C16/26 , G11C16/34 , G11C16/08 , G11C16/10
Abstract: PURPOSE: A non-volatile memory device and a memory system having the same are provided to perform writing in an optimum condition by selecting an optimum writing condition. CONSTITUTION: A cell array(110) comprises a plurality of memory cells formed in the cross-domain of a plurality of bit lines and word lines. An address decoder(120) selects one of word lines in response to the address. A write circuit(130) program data in memory cells connected to the selected word line. A control circuit(140) controls an address decoder and a write circuit to perform a plurality of band program operations successively. The control circuit selects a wiring condition of a next band program in a band program operation.
Abstract translation: 目的：提供一种非易失性存储器件和具有该非易失性存储器件的存储器系统，以通过选择最佳写入条件在最佳条件下执行写入。 构成：单元阵列（110）包括在多个位线和字线的交叉域中形成的多个存储单元。 地址解码器（120）响应于地址选择字线之一。 写入电路（130）连接到所选字线的存储器单元中的程序数据。 控制电路（140）控制地址解码器和写入电路，以连续执行多个频带编程操作。 控制电路在频带编程动作中选择下一频带节目的配线条件。
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公开(公告)号：KR100733954B1
公开(公告)日：2007-06-29
申请号：KR1020060054029
申请日：2006-06-15
Applicant: 삼성전자주식회사
Abstract: A flash memory device with an improved scan structure is provided to minimize layout area of a multi-buffer block by performing a scan operation of 2-word data through one scan logic. A flash memory device with an improved scan structure includes a memory cell array and a multi-buffer block which stores program data to be stored in the memory cell array. The multi-buffer block includes a plurality of buffer circuits(600_0) each of which stores at least 2-word data. Each buffer circuit includes a plurality of registers which stores two corresponding data bits of 2-word data, and scan logics(635) constituted to scan the number of program data of first word data among 2-word data during a first scan period and to scan the number of program data of a second word-data of the 2-word data on the ground of the number of program data of the first word data during a second scan period.
Abstract translation: 提供具有改进的扫描结构的闪存器件，以通过经由一个扫描逻辑执行2字数据的扫描操作来最小化多缓冲器块的布局面积。 具有改进的扫描结构的闪存器件包括存储器单元阵列和存储要存储在存储器单元阵列中的程序数据的多缓冲器块。 多缓冲器块包括多个缓冲器电路（600_0），每个缓冲器电路存储至少2个字的数据。 每个缓冲器电路包括多个寄存器，其存储两个相应的2字数据的数据位，以及扫描逻辑（635），构成为在第一扫描周期期间扫描2字数据中的第一字数据的编程数据的数量， 在第二扫描周期期间基于第一字数据的多个编程数据扫描2字数据的第二字数据的编程数据的数量。
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Patent Agency Ranking
公开(公告)号：KR100719368B1
公开(公告)日：2007-05-17
申请号：KR1020050055906
申请日：2005-06-27
Applicant: 삼성전자주식회사
IPC: G11C16/12
CPC classification number: G11C16/12 , G11C16/3454 , G11C16/3459
Abstract: 본 발명의 플래시 메모리 장치의 적응적 ISPP방법은 적어도 하나 이상의 패스 셀이 발생할 때까지 제 1 프로그램 전압과 제 1 검증시간으로 프로그램-검증 루프를 실행하는 제 1 프로그램 단계와; 적어도 하나 이상의 패스 셀이 발생한 이후 제 2 프로그램 전압과 제 2 검증시간으로 프로그램-검증 루프를 실행하는 제 2 프로그램 단계를 포함하되, 상기 제 2 프로그램 단계는 상기 적어도 하나 이상의 패스 셀에 대하여 한번 더 검증동작이 이루어지도록 제어한다. 상술한 바와 같은 본 발명의 프로그램 방법은 프로그램 이후에 상측 및 하측의 문턱전압 산포의 효과적 억제를 가능하게 한다.
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公开(公告)号：KR1020070000525A
公开(公告)日：2007-01-03
申请号：KR1020050055906
申请日：2005-06-27
Applicant: 삼성전자주식회사
IPC: G11C16/12
CPC classification number: G11C16/12 , G11C16/3454 , G11C16/3459
Abstract: An apparatus and a method for adaptive ISPP(Incremental Step Pulse Programming) in a flash memory device are provided to improve threshold voltage dispersion of a cell without much loss of program time during a program operation of the flash memory, by comprising a voltage generator supplying a first or a second program voltage to a word line. A flash memory device includes a plurality of memory cells. A voltage generator(10) supplies a first or a second program voltage to word lines of the memory cells. Sense amplifiers are connected to each of bit lines of the memory cells to sense a first or a second verify time, and output the results as pass signals, respectively. A program control part(60) controls to convert the verify time of the sense amplifier and the program voltage of the voltage generator by detecting that at least more than one cells passes, referring to the pass signals. The program control part controls to perform one or more verify operation to the cells with the converted verify time.
Abstract translation: 提供了一种用于闪速存储器件中的自适应ISPP（增量式步进脉冲编程）的装置和方法，用于通过包括提供电压的电压发生器来提供单元的阈值电压色散，而不会在闪存的编程操作期间的编程时间大量损失 第一或第二编程电压到字线。 闪存器件包括多个存储器单元。 电压发生器（10）将第一或第二编程电压提供给存储单元的字线。 感测放大器连接到存储器单元的每个位线以感测第一或第二验证时间，并将结果分别作为通过信号输出。 参考通过信号，程序控制部分（60）通过检测至少一个以上的单元通过来控制转换感测放大器的验证时间和电压发生器的编程电压。 程序控制部分控制对转换的验证时间的单元执行一个或多个验证操作。
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公开(公告)号：KR1020030094735A
公开(公告)日：2003-12-18
申请号：KR1020020032005
申请日：2002-06-07
Applicant: 삼성전자주식회사
Inventor： 김수한
IPC: H01L27/108
Abstract: PURPOSE: A method for fabricating a semiconductor memory device is provided to improve a refresh characteristic by forming a storage node directly connected to a contact plug. CONSTITUTION: An insulation layer is formed on a substrate(100) having a plurality of bitline structures(132). The insulation layer is etched to form the first contact hole with the first line width and such a depth to expose the bitline structure. The insulation layer on the lower surface of the first contact hole is etched to expose the surface of the substrate and form the second contact hole with the second line width smaller than the first line width. A conductive layer for a lower electrode is uniformly formed on the sidewall of the first contact hole, the bitline structure, the sidewall of the second contact hole and the substrate to form a storage node. The insulation layer is etched until the upper surface of the bitline structure is exposed. A dielectric layer and a plate electrode are sequentially formed on the storage node.
Abstract translation: 目的：提供一种用于制造半导体存储器件的方法，通过形成直接连接到接触插头的存储节点来提高刷新特性。 构成：在具有多个位线结构（132）的基板（100）上形成绝缘层。 蚀刻绝缘层以形成具有第一线宽度的这种第一接触孔和暴露位线结构的这样的深度。 蚀刻第一接触孔的下表面上的绝缘层，露出基板的表面，形成第二接线孔，第二线宽小于第一线宽。 用于下电极的导电层均匀地形成在第一接触孔的侧壁，位线结构，第二接触孔的侧壁和基板上，以形成存储节点。 绝缘层被蚀刻直到位线结构的上表面露出。 在存储节点上依次形成电介质层和平板电极。
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公开(公告)号：KR1019990027902A
公开(公告)日：1999-04-15
申请号：KR1019970050432
申请日：1997-09-30
Applicant: 삼성전자주식회사
Inventor： 김수한
IPC: H01L21/027
Abstract: 본 발명은 반도체 장치에 관한 것으로, 특히 국부적인 포커스 디펙트 발생을 줄일 수 있는 반도체 장치의 노광 척에 관한 것이다. 노광 척은 웨이퍼를 진공으로 클램핑하기 위한 부분과 웨이퍼의 평탄도에 영향을 미치는 부분만으로 되어 있다. 즉, 웨이퍼의 가장자리와만 접하도록 그 중앙부가 뚫린 형태로 설계되어 있다.
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公开(公告)号：KR1019930009012A
公开(公告)日：1993-05-22
申请号：KR1019910017326
申请日：1991-10-02
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: 동일 반도체 기판상에 서로다른 또는 동일 폭을 갖는 트랜치에 의한 소자분리영역을 갖는 반도체 장치 제조공정에서, 반도체 기판상에 절연층을 형성하여 비활성영역(소자분리영역)에 대한 개구부를 형성하는 단계, 활성영역을 포위하는 환상의 트렌치 영역을 정의하기 위해 개구부 측벽에 상기 절연층과 다른 식각률의 스페이서를 형성하는 단계, 스페이서로 정의된 기판에 대해 스페이서와는 다른 식각률을 갖는 또다른 절연층을 형성하고 상기 스페이서를 식각하여 제거함으로써 이 영역에 대해 기판을 노출시키는 단계, 노출된 기판에 대해 트렌치를 형성하고 상기 개구부 형성시 사용된 절연층과 동일 재질의 절연층을 침적형성하여 트렌치를 매립하고 비활성영역상의 절연층 양측벽에 대해 스페이서를 형성하므로써 활성영역을 포위하는 환상의 트렌치가 형성된 소자분리영역을 갖는 것을 특징으로 하는 반도체 장치 제조방법.
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