公开(公告)号：KR100460337B1

公开(公告)日：2005-01-17

申请号：KR1019980003113

申请日：1998-02-04

Applicant: 삼성전자주식회사

Inventor： 최수열 ,  류근복

IPC: H01L21/68

Abstract: PURPOSE: A method for analyzing a semiconductor wafer is provided to improve reliability of analysis data according to yield by precisely analyzing the cause of yield in fabricating a semiconductor device. CONSTITUTION: A fabrication process is performed to form a predetermined pattern on a wafer. The electrical state of chips constituting the wafer having the predetermined pattern is inspected to check the yield of the chip. An EDS(electrical die sorting) process is performed to inspect the type of a defect according to the inspection and the distribution of the defect existing on the wafer. A strip process is performed to remove the predetermined pattern formed on the wafer. The surface of the wafer from which the predetermined pattern is stripped is polished by a polishing process. An analysis process is performed to analyze the type of the defect existing on the wafer and the distribution of the defect.

公开(公告)号：KR1020010016973A

公开(公告)日：2001-03-05

申请号：KR1019990032246

申请日：1999-08-06

Applicant: 삼성전자주식회사

Inventor： 이곤섭 ,  박재근 ,  박정민 ,  류근복

IPC: H01L21/302

Abstract: PURPOSE: A method for manufacturing a perfect fully depletion(PFD) smart-cut wafer is provided to form a wafer of which a surface is smooth and a surface silicon layer is uniform in thickness, by preventing a vacancy and an interstitial conglomeration, thereby minimizing a crystal originated particle(COP) and a large dislocation of the surface silicon layer. CONSTITUTION: A pure single crystal wafer having no vacancy and interstitial conglomeration is used as the first substrate, and hydrogen ions are implanted into a predetermined depth of the first substrate. An oxide layer(16) is grown on the second substrate(14) by a predetermined thickness, wherein the second substrate is the same as the first substrate. The first substrate is stacked on the oxide layer, and an annealing process is performed in a nitrogen atmosphere at a temperature from 400 to 600 deg.C, so that an oxide silicon layer is grown on interfaces between the oxide layer and the first substrate and between the oxide layer and the second substrate while they are bonded. An upper end of the first substrate is split to cut the first substrate at a position where hydrogen ions are implanted. The resultant structure cut at the ion implanting position is annealed in an H2 or Ar atmosphere at a temperature of 1200 deg.C or higher. A thermal oxide is performed regarding the annealed first substrate at a temperature of 1000 deg.C or higher by a wet or dry oxide method, to form a surface oxide layer(18) on the first substrate.

Abstract translation: 目的：提供一种用于制造完全耗尽（PFD）智能切割晶片的方法，通过防止空位和间隙聚集形成表面光滑的表面硅层和厚度均匀的晶片，从而最小化 晶体起始粒子（COP）和表面硅层的大位错。 构成：使用没有空位和间隙聚集的纯单晶晶片作为第一衬底，并将氢离子注入第一衬底的预定深度。 在第二基板（14）上生长预定厚度的氧化物层（16），其中第二基板与第一基板相同。 第一衬底层叠在氧化物层上，并且在氮气气氛中在400〜600℃的温度下进行退火处理，使得在氧化物层和第一衬底之间的界面上生长氧化硅层， 在氧化物层和第二基板之间粘合时。 第一基板的上端被分割以在植入氢离子的位置处切割第一基板。 在离子注入位置处切割的所得结构在H2或Ar气氛中在1200℃或更高的温度下退火。 通过湿式或干式氧化法在1000℃以上的温度下对退火的第一基板进行热氧化，在第一基板上形成表面氧化物层（18）。

公开(公告)号：KR1020010027009A

公开(公告)日：2001-04-06

申请号：KR1019990038564

申请日：1999-09-10

Applicant: 삼성전자주식회사

Inventor： 박재근 ,  이곤섭 ,  박정민 ,  류근복

IPC: H01L21/316

Abstract: PURPOSE: A method for fabricating a perfect-fully-depletion(PFD) separation-by-implantation-oxide(SIMOX) wafer is provided to improve integration and reliability, by forming the PFD SIMOX wafer which does not have threading dislocation and an agglomeration. treading CONSTITUTION: A single crystal silicon wafer without crystal originated particles(COP) is induced as a substrate, wherein the single crystal silicon wafer does not have a vacancy and an interstitial agglomeration. Oxygen ions of 3.5-4.4 E16/square centimeter are implanted into the substrate to form an oxide layer inside the substrate. The substrate implanted with the oxygen ions are annealed at a temperature of 1200 deg.C in a mixture atmosphere of N2 gas and O2 gas so that the vacancy on the oxide layer is not concentrated on a position and an agglomeration is prevented. An upper surface of the annealed substrate is polished.

Abstract translation: 目的：通过形成不具有穿透位错和聚集的PFD SIMOX晶片，提供了一种用于制造完全耗尽（PFD）分离 - 注入氧化物（SIMOX）晶片的方法，以提高整合性和可靠性。 构成方案：将不含晶体原始颗粒（COP）的单晶硅晶片作为基板，其中单晶硅晶片不具有空位和间隙聚集。 将3.5-4.4E16 /平方厘米的氧离子注入衬底中以在衬底内部形成氧化物层。 注入氧离子的基板在N2气和O2气体的混合气氛中在1200℃的温度下退火，使得氧化物层上的空位不集中在位置上，并且防止凝聚。 抛光退火基板的上表面。

公开(公告)号：KR1020010016974A

公开(公告)日：2001-03-05

申请号：KR1019990032247

申请日：1999-08-06

Applicant: 삼성전자주식회사

Inventor： 류근복 ,  심태헌 ,  박재근 ,  최수열

IPC: H01L21/30

Abstract: PURPOSE: A method for manufacturing a wafer is provided to improve productivity and to reduce a manufacturing cost, by decreasing the number of processing steps for fabricating the wafer of which resistivity is improved. CONSTITUTION: A single silicon ingot is grown from a silicon melted solution. The ingot is sliced to a wafer of a predetermined thickness. A surface of the sliced wafer is planarized. A foreign substance on the surface of the polished wafer is etched away. The etched wafer is cleaned with deionized(DI) water. The surface of the cleaned wafer is polished. The polished wafer is lastly cleaned by DI water. The lastly-cleaned wafer is packed for shipment. The wafer is initially oxidized at a temperature of 900 deg.C by a manufacturer for making a semiconductor device.

Abstract translation: 目的：提供一种用于制造晶片的方法，通过减少用于制造电阻率提高的晶片的处理步骤的数量来提高生产率并降低制造成本。 构成：单个硅锭从硅熔融溶液中生长。 将锭切成预定厚度的晶片。 切片晶片的表面被平坦化。 在抛光晶片的表面上的异物被蚀刻掉。 用去离子（DI）水清洗蚀刻后的晶片。 清洁的晶片的表面被抛光。 抛光的晶片最后用去离子水清洗。 最后清洗的晶圆被装运。 晶片最初由制造半导体器件的制造商在900℃的温度下被氧化。

公开(公告)号：KR100308183B1

公开(公告)日：2001-11-01

申请号：KR1019990033715

申请日：1999-08-16

Applicant: 삼성전자주식회사

Inventor： 박재근 ,  이곤섭 ,  심태헌 ,  류근복

IPC: H01L21/00

Abstract: 목적 : 본발명은고유게터링퓨어(Intrinsic Gettering Pure)를실현한실리콘웨이퍼(Intrinsic Gettering Pure Silicon Wafer)의제조방법에관한것이다. 구성 : 본발명에의한웨이퍼의제조방법은, 인터스티셜집괴를방지할수 있도록충분히높으나, 베이컨시집괴를잉곳의축방향을따라서베이컨시-풍부영역내로제한시킬수 있도록충분히낮은인상속도(Pull Rate) 프로파일에서핫존로내의실리콘용융물로부터잉곳을축방향으로인상하여서제조된무결점단결정실리콘잉곳을성장하는공정, 상기잉곳으로부터소정두께의웨이퍼로슬라이싱하는공정, 상기슬라이싱된 웨이퍼면을연마하여평탄화하는공정, 상기연마된웨이퍼면의이물질을에칭의방법으로제거하는공정, 상기에칭된웨이퍼를 1200℃이상의고온으로아르곤분위기에서급속열처리(Rapid Temperature Annealing)하는방법으로도우너를킬링하는공정, 상기도우너의킬링을마친웨이퍼를순수를사용하여세정하는공정, 상기세정된웨이퍼면을폴리싱하는공정, 상기폴리싱된웨이퍼를순수를사용하여최종세정하는공정, 및상기최종세정된웨이퍼를패킹하는공정으로이루어진다. 효과 : 반도체소자의수율및 신뢰성을향상시키는데적당한웨이퍼를공급할수 있는효과가있다.

公开(公告)号：KR1020010017957A

公开(公告)日：2001-03-05

申请号：KR1019990033715

申请日：1999-08-16

Applicant: 삼성전자주식회사

Inventor： 박재근 ,  이곤섭 ,  심태헌 ,  류근복

IPC: H01L21/00

Abstract: PURPOSE: A method for making a pure silicon wafer is provided to realize an intrinsic gettering of crystal defects such as crystal originated particles or dislocation defects. CONSTITUTION: The method begins with a step(S102) of growing a defect-free monocrystalline silicon ingot in which the ingot is pulled from a molten silicon in a hot zone furnace within a pull rate higher enough to prevent interstitial agglomerates and lower enough to restrict vacancy agglomerates to a vacancy-rich region. The ingot is then sliced into a plurality of wafers with a definite thickness(S102). Thereafter, a sliced surface of the wafer is lapped and planarized(S103), and remaining particles on the wafer surface are removed by a plasma etching(S104). After that, the wafer is subjected to a rapid temperature annealing under an argon atmosphere at a temperature of 1200 deg. C or more to kill donors(S105). The wafer is then cleaned(S106), polished(S107), cleaned again(S108), and finally packed(S109).

Abstract translation: 目的：提供一种制造纯硅晶片的方法，以实现晶体缺陷如晶体起始粒子或位错缺陷的固有吸收。 构成：该方法开始于生长无缺陷的单晶硅锭的步骤（S102），其中在热区炉中将锭从熔融硅中拉出，其拉拔速率更高以防止间隙附聚物并且足够低以限制 空缺聚集到一个空缺丰富的地区。 然后将锭切成多个具有确定厚度的晶片（S102）。 然后，对晶片的切片面进行研磨并平坦化（S103），通过等离子体蚀刻除去晶片表面上的剩余粒子（S104）。 之后，在1200℃的温度下，在氩气氛下对晶片进行快速退火。 C以上杀死捐助者（S105）。 然后将晶片清洗（S106），抛光（S107），再次清洗（S108），最后包装（S109）。

公开(公告)号：KR1019990070082A

公开(公告)日：1999-09-06

申请号：KR1019980004729

申请日：1998-02-17

Applicant: 삼성전자주식회사

Inventor： 박정민 ,  조규철 ,  류근복

IPC: H01L21/66

Abstract: 본 발명은 COP 및 반도체 디바이스 일드 사이의 상관관계 시뮬레이팅 방법에 관한 것으로, 본 발명에서는 일정한 연산식을 통해 COP 및 디바이스 일드 사이의 상관관계를 연산한 후 이를 이용하여 COP 및 디바이스 일드 사이의 상관관계가 시뮬레이팅 되도록 함으로써, 작업자가 복잡한 실험과정을 거치지 않고도 디바이스의 일드를 미리 예측하여, COP의 수를 적절히 억제시킬 수 있도록 한다.

公开(公告)号：KR100334576B1

公开(公告)日：2002-05-03

申请号：KR1019990032247

申请日：1999-08-06

Applicant: 삼성전자주식회사

Inventor： 류근복 ,  심태헌 ,  박재근 ,  최수열

IPC: H01L21/30

Abstract: 목적: 본발명은비저항을향상시킬수 있고양호한생산성으로저렴하게제조될수 있는실리콘웨이퍼의제조방법을제공하고자한다. 구성: 본발명의구성으로서, 웨이퍼공급업체에서의웨이퍼제조공정은실리콘용융액으로부터단결정실리콘잉곳을그로잉하는단계, 상기잉곳으로부터소정두께의웨이퍼로슬라이싱하는단계, 상기슬라이싱된 웨이퍼면을연마하여평탄화하는단계, 상기연마된웨이퍼면의이물질을에칭의방법으로제거하는단계, 상기에칭된웨이퍼를순수를사용하여세정하는단계, 상기세정된웨이퍼면을폴리싱하는단계, 상기폴리싱된웨이퍼를순수를사용하여최종세정한후 패킹하여출하하는단계로순차행하고, 상기웨이퍼공급업체에서출하된웨이퍼에반도체디바이스를제조하는디바이스제조업체의최초공정은웨이퍼를 900℃이상의온도로초기산화시키는단계로행함이특징이다.

公开(公告)号：KR1020000061813A

公开(公告)日：2000-10-25

申请号：KR1019990011173

申请日：1999-03-31

Applicant: 삼성전자주식회사

Inventor： 홍종혁 ,  이곤섭 ,  조성훈 ,  류근복

IPC: H01L21/304

Abstract: PURPOSE: A manufacturing method of a wafer is to improve the flatness of wafer by grinding the uneven surface of wafer being generated in an etching process after terminating an etching process. CONSTITUTION: A manufacturing method of a wafer comprises: a first lapping step of lapping both sides of the severed wafer; a step of etching the surface of the wafer thus lapped using an etchant; a second lapping step of lapping the surface of wafer thus etched so that it has a desired flatness; and a step of polishing of finely polishing the surface of the wafer thus lapped. The surface of the wafer is lapped more finely in the second lapping step than in the first polishing step.

Abstract translation: 目的：晶片的制造方法是通过在终止蚀刻工艺之后通过研磨在蚀刻工艺中产生的晶片的不平坦表面来提高晶片的平坦度。 构成：晶片的制造方法包括：研磨切断的晶片的两侧的第一研磨步骤; 使用蚀刻剂蚀刻如此研磨的晶片的表面的步骤; 研磨如此蚀刻的晶片的表面以使其具有期望的平坦度的第二研磨步骤; 以及研磨精细研磨如此研磨的晶片的表面的步骤。 在第二研磨步骤中，晶片的表面比第一抛光步骤更细。

公开(公告)号：KR1020000020759A

公开(公告)日：2000-04-15

申请号：KR1019980039507

申请日：1998-09-23

Applicant: 삼성전자주식회사

Inventor： 박재근 ,  조규철 ,  이곤섭 ,  류근복

IPC: H01L21/00

Abstract: PURPOSE: A fabrication method of a test wafer without COP(Crystal Orinated Particle) is provided to count the number of particles on its surface easily. CONSTITUTION: The method comprises the steps of: putting a poly crystalline silicon into a melting pot of which temperature could be controlled, and melting it; descending an arm including a mono crystalline piece to inside a melting pot to result in the mono crystalline piece to contact with a poly crystalline silicon; reducing the speed of the arm down to average speed under 0.35mm/min when the piece begins to melt; forming a mono crystalline silicon bar which has the same crystalline structure like the mono crystalline piece through melting silicon attached to the mono crystalline piece solidifies resulted from ascending the arm to the upper part of the poly crystalline silicon; cutting the silicon bar in slice and polishing it. Therefore, a 12 inches' test wafer without COP is fabricated.

Abstract translation: 目的：提供没有COP（晶体粒子）的测试晶片的制造方法来容易地计数其表面上的颗粒数。 构成：该方法包括以下步骤：将多晶硅放入可以控制温度的熔池中并熔化; 将包括单晶片的臂下降到熔池内部，导致单晶片与多晶硅接触; 当片开始融化时，将手臂的速度降低到0.35mm / min以下的平均速度; 通过熔融连接到单晶片上的硅固化，形成具有与单晶片相同的晶体结构的单晶硅棒，其由臂上升到多晶硅的上部; 切片硅片并抛光。 因此，制造了没有COP的12英寸测试晶片。