-
公开(公告)号：KR100080843B1
公开(公告)日：1994-12-28
申请号：KR1019910014099
申请日：1991-08-14
Applicant: 삼성전자주식회사
IPC: G11C11/404
-
公开(公告)号：KR1019940008294B1
公开(公告)日：1994-09-10
申请号：KR1019910014099
申请日：1991-08-14
Applicant: 삼성전자주식회사
IPC: G11C11/404
Abstract: The data transmission circuit gives speed-up based on using bit lines directly connected to the gates of output transistors during data transmission in dynamic RAM and gives large scale integration with common I/O lines. The circuit comprises bit lines BL, BL (65)(66) connected to a memory cell (51), transistors (61)(62)(63)(64) for data input, transistors (57)(58) for data output, transistors (53)(54)(59)(60) for separation of electric connection, a transistor (56) for electric discharge to make a voltage level applied to other channel an earth voltage level, a sense amplifier (55) for amplifying the voltage difference between the bit lines BL, BL (65)(66), a signal (CSL) for selecting a memory cell (51).
Abstract translation: 数据传输电路基于在动态RAM中的数据传输期间使用直接连接到输出晶体管的栅极的位线，并提供与普通I / O线的大规模集成的加速。 电路包括连接到存储单元（51）的位线BL，BL（65）（66），用于数据输入的晶体管（61）（62）（63）（64），用于数据输出的晶体管 ，用于分离电连接的晶体管（53）（54）（59）（60），用于放电以使其他通道施加电压电平的晶体管（56）为接地电压电平;用于放大的读出放大器 位线BL，BL（65）（66）之间的电压差，用于选择存储单元（51）的信号（CSL）。
-
公开(公告)号：KR1019940004517B1
公开(公告)日：1994-05-25
申请号：KR1019910014098
申请日：1991-08-14
Applicant: 삼성전자주식회사
IPC: G11C11/407
Abstract: a ground transistor having one terminal of a channel connected to a ground voltage, for setting a potential connected to the other terminal of the channel to a ground voltage level; first and second input transistors each having a channel connected between a bit line and a common input/output line and each having a gate connected to a control gate; and first and second output transistors each having a channel connected between the other terminal of the channel of the ground transistor and the common input/output line and each having a gate connected to the bit line. The circuit improves data tranmission speed.
Abstract translation: 接地晶体管，其具有连接到接地电压的沟道的一个端子，用于将连接到所述沟道的另一端子的电位设置为接地电压电平; 第一和第二输入晶体管，每个具有连接在位线和公共输入/输出线之间的通道，并且每个具有连接到控制栅极的栅极; 以及第一和第二输出晶体管，每个具有连接在接地晶体管的沟道的另一个端子和公共输入/输出线之间的沟道，并且每个具有连接到位线的栅极。 该电路提高了数据传输速度。
-
公开(公告)号：KR1019930022363A
公开(公告)日：1993-11-24
申请号：KR1019920006954
申请日：1992-04-24
Applicant: 삼성전자주식회사
Inventor： 민병혁
IPC: G11C7/00
Abstract: 본 발명은 반도체 메모리 장치에서 특히 메모리 셀로부터 독출된 데이타를 칩 외부로 출력시키는 데이타 출력버퍼에 관한 것으로, 본 발명에 의한 데이타 출력버퍼는 입력단과 출력용 풀업 트랜지스터의 사이에 상기 출력용 풀업 트랜지스터를 제어하기 위한 소정의 레벨변환회로(100)를 구비하므로서, 회로구성이 콤팩트하여 고집적화에 유리하고, 또한 출력동작이 안정화되고, 또한 저전원전압 상태하에서도 동작속도의 고속화가 이루어지므로서, 특히 내부전원전압을 사용하는 반도체 메모리 장치의 성능을 향상시키는 효과가 있다.
-
公开(公告)号：KR1019930005024A
公开(公告)日：1993-03-23
申请号：KR1019910014098
申请日：1991-08-14
Applicant: 삼성전자주식회사
IPC: G11C11/407
Abstract: 내용 없음.
-
Patent Agency Ranking
公开(公告)号：KR100318540B1
公开(公告)日：2001-12-22
申请号：KR1019990007497
申请日：1999-03-08
Applicant: 삼성전자주식회사
IPC: G02F1/136 , G02F1/1343
Abstract: 기판위에게이트선, 게이트전극을포함하는게이트배선과공통신호선, 공통전극을포함하는공통배선과다수의게이트선을연결하는방전용게이트선연결부와제1 내지제3 검사용데이터선연결부를형성하고, 이들을위에게이트절연막을형성한다. 게이트전극위의게이트절연막위에는반도체층과저항접촉층을형성하고, 이어저저항을가지는알루미늄계열의도전막을포함하는제1 금속층으로소스및 드레인전극, 데이터선, 데이터패드를포함하는데이터배선과화소신호선, 화소전극을포함하는화소배선과다수의데이터선을연결하는방전용게이트선연결부와제1 및제2 검사용게이트선연결부를형성하고, 이들을덮는보호막을형성한다. 이어, 보호막위에제2 금속층으로용장(redundancy) 데이터선, 용장데이터패드를포함하는용장데이터배선과용장게이트패드를형성한다. 용장데이터배선은보호막에형성된접촉창을통해데이터배선과전기적으로연결되며, 용장게이트패드는게이트절연막과보호막에형성된접촉창을통해게이트패드와전기적으로연결된다. 또한, 제1 및제2 검사용게이트선연결부는보호막또는게이트절연막에형성된접촉구멍을통하여홀수및 짝수번째게이트선과각각연결되며제1 내지제3 검사용데이터선연결부는각각 3n-2, 3n-1, 3n 번째데이터선과각각연결된다.
-
公开(公告)号：KR1020010055970A
公开(公告)日：2001-07-04
申请号：KR1019990057314
申请日：1999-12-13
Applicant: 삼성전자주식회사
Inventor： 민병혁
IPC: G02F1/136
Abstract: PURPOSE: A thin film transistor substrate for an LCD(liquid crystal display) and a fabricating method thereof are to efficiently discharge static electricity and also facilely test an array thereof, thereby simply detecting defect and short of a pixel. CONSTITUTION: A gate wiring is formed on an insulating substrate, and has a plurality of gate lines for transferring a scanning signal, the first gate electrode(211) which is connected with the gate line and a gate pad which is connected to the gate line to receive the scanning signal from an outside. A plurality of data line testing signal lines are formed on the substrate to be separated from the gate wiring. A plurality of second and third gate electrodes are formed on the substrate. A gate insulating film covers the gate wiring, the data line testing signal line and the second and third gate electrode(212). The first to second semiconductor patterns are formed on the gate insulating film of the first to third gate electrode. The first to third resistive contact layer patterns are formed on the first to third semiconductor patterns. A data wiring has a plurality of data lines, a source electrode(611,612), a drain electrode(621,622) and a data pad. A plurality of gate line testing signal lines are separated from the data line. The first discharging line is formed on the insulating substrate.
Abstract translation: 目的：用于LCD（液晶显示器）的薄膜晶体管基板及其制造方法是有效地排出静电，并且还易于测试其阵列，从而简单地检测像素的缺陷和缺陷。 构成：在绝缘基板上形成栅极布线，并且具有用于传送扫描信号的多条栅极线，与栅极线连接的第一栅电极（211）和与栅极线连接的栅极焊盘 从外部接收扫描信号。 多个数据线测试信号线形成在衬底上以与栅极布线分离。 在基板上形成多个第二和第三栅电极。 栅极绝缘膜覆盖栅极布线，数据线测试信号线以及第二和第三栅电极（212）。 第一至第二半导体图案形成在第一至第三栅电极的栅极绝缘膜上。 第一至第三电阻接触层图案形成在第一至第三半导体图案上。 数据线具有多条数据线，源电极（611,612），漏电极（621,622）和数据焊盘。 多条栅线测试信号线与数据线分离。 第一放电线形成在绝缘基板上。
-
公开(公告)号：KR1020000060802A
公开(公告)日：2000-10-16
申请号：KR1019990009421
申请日：1999-03-19
Applicant: 삼성전자주식회사
IPC: G02F1/136 , G02F1/1343
Abstract: PURPOSE: A thin film transistor substrate for a liquid crystal display device is provided to be capable of repairing a line short circuit at an intersection portion between the gate line and the data line. CONSTITUTION: A thin film transistor substrate for a liquid crystal display device comprises a plurality of gate lines(110) which are formed on an insulation substrate(10) in a horizontal direction. Dual common electrode lines(120,140) are formed between adjacent gate lines(110) in parallel with the gate lines(110). A plurality of common electrodes(140) is formed so as to connect the dual common electrode lines(120,140) in a vertical direction. The gate lines, the dual common electrode lines and the common electrode are covered by a gate insulation film(20). A plurality of repair patterns(210) is formed on the gate insulation film(20) so as to be overlapped one or all of common electrodes(120,130) adjacent to the gate line(110).
Abstract translation: 目的：提供一种用于液晶显示装置的薄膜晶体管基板，以能够修复栅极线和数据线之间的交叉部分处的线路短路。 构成：用于液晶显示装置的薄膜晶体管衬底包括在绝缘衬底（10）上沿水平方向形成的多条栅极线（110）。 在相邻的栅极线（110）之间与栅极线（110）平行地形成双公共电极线（120,140）。 多个公共电极（140）形成为在垂直方向上连接双公共电极线（120,140）。 栅极线，双公共电极线和公共电极被栅绝缘膜（20）覆盖。 多个修复图案（210）形成在栅极绝缘膜（20）上，以便与邻近栅极线（110）的一个或所有公共电极（120,130）重叠。
-
公开(公告)号：KR100177785B1
公开(公告)日：1999-03-20
申请号：KR1019960002634
申请日：1996-02-03
Applicant: 삼성전자주식회사
IPC: H01L29/70
CPC classification number: H01L29/0847 , H01L29/6675 , H01L29/7831 , H01L29/7833 , H01L29/78621 , H01L29/78645 , H01L29/788
Abstract: A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate. The transistor may be formed by patterning a photoresist layer and a gate layer to form a main gate and first and second sub gates, reflowing the photoresist into the lateral space between the main gate and the first and second sub gates, etching the gate insulating layer using the reflowed photoresist as a mask, and implanting ions into the substrate to form source and drain regions using the etched gate insulating layer as a mask.
-
-
-
-
-
-
-
-
-
Search Results
34
records
(took 0.025 seconds)
