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公开(公告)号：KR101435520B1
公开(公告)日：2014-09-01
申请号：KR1020080078519
申请日：2008-08-11
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: G11C16/0483 , G11C5/06 , H01L21/0337 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11524 , H01L27/11526 , H01L27/11531 , H01L27/11548 , H01L27/1157 , H01L27/11573 , H01L27/11575
Abstract: 다양한 폭을 가지는 패턴들을 동시에 형성하면서 일부 영역에서는 더블 패터닝 기술에 의해 패턴 밀도를 배가시키는 반도체 소자의 패턴 형성 방법을 개시한다. 본 발명에 따른 공정에서는 기판상의 듀얼 마스크층을 패터닝하여 제1 영역에는 제1 마스크 패턴을 형성하고, 제2 영역에는 제1 마스크 패턴보다 폭이 큰 제2 마스크 패턴을 형성한다. 제1 마스크 패턴의 양 측벽을 덮는 제1 스페이서와 제2 마스크 패턴의 양 측벽을 덮는 제2 스페이서를 동시에 형성한다. 제1 마스크 패턴을 제거한 후, 제1 영역에서는 제1 스페이서를 식각 마스크로 이용하고 제2 영역에서는 제2 마스크 패턴 및 제2 스페이서를 식각 마스크로 이용하여 제1 영역 및 제2 영역에서 동시에 기판을 식각한다.
패턴, 폭, 3차원 식각 효과, 가변 마스크 패턴, 듀얼 마스크층, 스페이서-
公开(公告)号：KR1020110087976A
公开(公告)日：2011-08-03
申请号：KR1020100007672
申请日：2010-01-28
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L21/28 , H01L27/115
CPC classification number: H01L27/11526 , H01L21/0337 , H01L21/0338 , H01L21/28132 , H01L21/31144 , H01L21/76816 , H01L27/11529 , H01L21/76205
Abstract: PURPOSE: A formation method of a wiring structure for a semiconductor device and a manufacturing method of a non-volatile memory device using the same are provided to prevent a discordance of array by a distinct photo process and to improve the processing efficiency by forming a hard mask pattern with a double patterning technique by a single photo process in damascene process in order to form a wiring structure of the semiconductor device when a flash is buried. CONSTITUTION: A first region(A) and a second region(B) are prepared. An insulating layer(20), a hard mask layer(30), a sacrificing layer, and a variable mask layer are formed on a substrate including a plurality of lower part conductive constructs. A first reserves pattern comprises a first sacrificing layer pattern and a variable mask layer pattern which is laminated on the first region by patterning the sacrificing layer and the variable mask layer. A second reserves pattern comprises a second sacrificing layer pattern and a second mask layer pattern which is laminated on the second region. A first spacer and a second spacer are formed on the each side of the first and second reserves patterns at the same time. The first spacer leaves behind in the first region by eliminating the first reserves pattern. A first hard mask pattern which is arranged on the first region and a second hard mask pattern which is arranged on the second region are formed by eliminating the hard mask layer with an etching process using the first spacer, the second spacer, and the second reserves pattern as etching mask. A conductive pattern which fills a first trench and a second trench inside is formed.
Abstract translation: 目的：提供一种用于半导体器件的布线结构的形成方法和使用该半导体器件的非易失性存储器件的制造方法，以通过不同的光刻工艺防止阵列的不一致，并且通过形成硬的方法来提高加工效率 掩膜图案，通过在镶嵌工艺中的单一光刻工艺进行双重图案化技术，以便在埋入闪光体时形成半导体器件的布线结构。 构成：准备第一区域（A）和第二区域（B）。 在包括多个下部导电构造的基板上形成绝缘层（20），硬掩模层（30），牺牲层和可变掩模层。 第一保留图案包括通过图案化牺牲层和可变掩模层而层压在第一区域上的第一牺牲层图案和可变掩模层图案。 第二保留图案包括层叠在第二区域上的第二牺牲层图案和第二掩模层图案。 在第一和第二储备图案的每一侧同时形成第一间隔物和第二间隔物。 第一个垫片通过消除第一个储备模式在第一个区域留下。 布置在第一区域上的第一硬掩模图案和布置在第二区域上的第二硬掩模图案通过使用第一间隔件，第二间隔件和第二间隔件的蚀刻工艺消除硬掩模层而形成 图案作为蚀刻掩模。 形成填充第一沟槽和第二沟槽内部的导电图案。
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公开(公告)号：KR1020110029228A
公开(公告)日：2011-03-23
申请号：KR1020090086808
申请日：2009-09-15
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: H01L21/76802 , H01L21/0334 , H01L21/0337 , H01L21/3081 , H01L21/311 , H01L21/31144 , H01L21/32139 , H01L21/76816 , H01L23/528 , H01L27/11521 , H01L2924/0002 , H01L2924/00 , H01L21/0338
Abstract: PURPOSE: A pattern structure and a forming method thereof are provided to reduce the process cost required for the formation of minute pattern structure by embodying the pattern structure including the pad with wide width by two times of photo process. CONSTITUTION: First and second patterns(122a, 122b) are arranged in parallel with the substrate. The first pattern comprises a first line pattern(E) which is extended in first direction with a first width and a first pad(G). The first extension line is connected to one end of the first line pattern. The first pad is connected to one end of the first extension line.
Abstract translation: 目的：提供图形结构及其形成方法，通过将包括具有宽宽度的垫的图案结构体现两倍的照相处理来减少形成微小图案结构所需的处理成本。 构成：第一和第二图案（122a，122b）与衬底平行布置。 第一图案包括在第一方向上以第一宽度延伸的第一线图案（E）和第一衬垫（G）。 第一条延长线连接到第一条线图案的一端。 第一垫连接到第一延长线的一端。
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公开(公告)号：KR101645720B1
公开(公告)日：2016-08-05
申请号：KR1020090086808
申请日：2009-09-15
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: H01L21/76802 , H01L21/0334 , H01L21/0337 , H01L21/3081 , H01L21/311 , H01L21/31144 , H01L21/32139 , H01L21/76816 , H01L23/528 , H01L27/11521 , H01L2924/0002 , H01L2924/00
Abstract: 패턴구조물및 이의형성방법에관한것으로, 상기패턴구조물은연장라인과, 상기연장라인의일 단부와연결되고, 상기연장라인보다넓은폭을갖고, 일측방으로돌출되는돌출부를갖는패드를포함한다. 상기패턴구조물은간단한공정에의해제조될수 있으며, 반도체소자에포함되는다양한미세패턴에사용될수 있다.
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公开(公告)号：KR1020130046812A
公开(公告)日：2013-05-08
申请号：KR1020110111411
申请日：2011-10-28
Applicant: 삼성전자주식회사
IPC: H01L27/10 , H01L21/8239 , H01L21/027
CPC classification number: H01L27/11517 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/0203 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/3276
Abstract: PURPOSE: A semiconductor device and a method for forming a pattern of the semiconductor device are provided to form a high precise pattern with a hyperfine width and a hyperfine interval by forming a pad on an extending unit with a wide space. CONSTITUTION: A second conductive line part(120) includes a plurality of second conductive lines and extending units(125A,125B). An interval of the extending unit is wider than an interval between first conductive lines. A pad part(130) is formed on the extending unit. The extending unit includes a plurality of pads. The pads are electrically connected to the second conductive lines.
Abstract translation: 目的：提供半导体器件和形成半导体器件的图案的方法，以通过在具有宽的空间的延伸单元上形成焊盘来形成具有超精细宽度和超精细间隔的高精度图案。 构成：第二导线部分（120）包括多个第二导线和延伸单元（125A，125B）。 延伸单元的间隔比第一导线之间的间隔宽。 在延伸单元上形成垫部件（130）。 延伸单元包括多个垫。 焊盘电连接到第二导线。
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Patent Agency Ranking
公开(公告)号：KR1020090065611A
公开(公告)日：2009-06-23
申请号：KR1020070132997
申请日：2007-12-18
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/115 , H01L21/31105 , H01L21/31116 , H01L21/31122 , H01L27/11521 , H01L21/76224 , H01L21/76838
Abstract: A method for forming a dielectric layer pattern by removing effectively a dielectric layer formed along a surface of a lower pattern and a method for manufacturing a non-volatile memory device using the same are provided to obtain a high coupling ratio by using a dielectric layer pattern having a high dielectric constant in a cell of the non-volatile memory device. A plurality of lower patterns(12) are formed on a substrate. A first dielectric layer is formed on sidewalls and upper surfaces of the lower patterns and a surface of the substrate. A mask pattern is formed on the first dielectric layer. A second dielectric layer(18) is thicker than the first dielectric layer. The first dielectric layer is removed from upper surfaces and upper sidewalls of the lower patterns. The first dielectric layer is re-deposited on the surface of the first dielectric layer between the lower patterns. A dielectric layer pattern is formed under the mask pattern by etching the second dielectric layer formed on the sidewalls of the lower patterns and the second dielectric layer formed on the substrate.
Abstract translation: 提供了通过有效地去除沿着下部图案的表面形成的电介质层来形成介电层图案的方法以及使用其形成非易失性存储器件的方法，以通过使用电介质层图案来获得高的耦合比 在非易失性存储器件的单元中具有高介电常数。 在基板上形成多个下图案（12）。 第一电介质层形成在下图案的侧壁和上表面以及基板的表面上。 在第一电介质层上形成掩模图案。 第二电介质层（18）比第一电介质层厚。 从下表面的上表面和上侧壁去除第一电介质层。 第一电介质层被重新沉积在下部图案之间的第一介电层的表面上。 通过蚀刻形成在下图案的侧壁上的第二电介质层和形成在基板上的第二电介质层，在掩模图案之下形成电介质层图案。
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公开(公告)号：KR1020080046349A
公开(公告)日：2008-05-27
申请号：KR1020060115689
申请日：2006-11-22
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/66825 , H01L21/28141 , H01L21/28273 , H01L21/31138 , H01L29/42324
Abstract: A method of manufacturing a non-volatile semiconductor device is provided to prevent the reduction of the threshold voltage by effectively removing the byproducts generated in a dry-etching for forming a dielectric layer pattern. A tunnel oxide layer is formed on a semiconductor substrate(100). A first conductive layer(120) is formed on the tunnel oxide layer. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer. A control gate(140a) is formed by patterning the second conductive layer. A spacer(150) is formed at the side of the control gate. A preliminary dielectric film pattern(130a) is formed by etching the dielectric layer partly. A dielectric pattern is formed by etching the preliminary dielectric film partly. The spacer is removed. A floating gate pattern and a tunnel oxide layer pattern are formed by patterning the first conductive layer and the tunnel oxide layer.
Abstract translation: 提供一种制造非挥发性半导体器件的方法，以通过有效地去除用于形成电介质层图案的干蚀刻中产生的副产物来防止阈值电压的降低。 隧道氧化物层形成在半导体衬底（100）上。 在隧道氧化物层上形成第一导电层（120）。 在第一导电层上形成电介质层。 在介电层上形成第二导电层。 通过图案化第二导电层形成控制栅极（140a）。 间隔件（150）形成在控制门的侧面。 通过部分地蚀刻介电层来形成预备电介质膜图案（130a）。 通过部分蚀刻预置电介质膜形成电介质图案。 移除间隔物。 通过图案化第一导电层和隧道氧化物层来形成浮栅图案和隧道氧化物层图案。
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公开(公告)号：KR1020170046892A
公开(公告)日：2017-05-04
申请号：KR1020150147061
申请日：2015-10-22
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/768
CPC classification number: H01L23/5283 , H01L21/76816 , H01L21/76829 , H01L21/76877 , H01L23/5226 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582
Abstract: 수직형메모리장치는기판, 기판의상면에대해수직방향으로연장하는복수의채널들, 채널들을감싸며수직방향으로서로이격되어적층되는복수의비금속게이트패턴들, 비금속게이트패턴들각각을둘러싸며상기수직방향으로서로이격되어적층되는복수의금속게이트패턴들을포함한다. 비금속게이트패턴및 금속게이트패턴의조합에의해수직형메모리장치의기계적, 전기적안정성이향상될수 있다.
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公开(公告)号：KR1020130021658A
公开(公告)日：2013-03-06
申请号：KR1020110084059
申请日：2011-08-23
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: G03F7/0035 , G03F7/00 , H01L21/0274 , B44C1/22
Abstract: PURPOSE: A method for forming a fine pattern is provided to reduce contraction between parallel wires due to a reverse loading effect and to secure sufficient misalignment margin when a pad is formed. CONSTITUTION: A first mold pattern(330) is formed on a first material layer(320). The first mold pattern includes a main pattern(332) and a separation-assist pattern(334a,334b,334c,334d). A first spacer mask of a first width is formed around the first mold pattern. A second mold pattern is formed by using the first spacer mask as an etch mask. A second spacer mask of a second width is formed around the second mold pattern. A target pattern is formed by using the second spacer mask as the etch mask.
Abstract translation: 目的：提供形成精细图案的方法，以减少由于反向加载效应引起的平行导线之间的收缩，并且当形成垫时确保足够的未对准余量。 构成：在第一材料层（320）上形成第一模具图案（330）。 第一模具图案包括主图案（332）和分离辅助图案（334a，334b，334c，334d）。 围绕第一模具图案形成第一宽度的第一间隔掩模。 通过使用第一间隔掩模作为蚀刻掩模形成第二模具图案。 围绕第二模具图案形成第二宽度的第二间隔掩模。 通过使用第二间隔掩模作为蚀刻掩模形成目标图案。
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公开(公告)号：KR101221598B1
公开(公告)日：2013-01-14
申请号：KR1020070132997
申请日：2007-12-18
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/115 , H01L21/31105 , H01L21/31116 , H01L21/31122 , H01L27/11521
Abstract: 유전막 패턴 형성 방법 및 이를 이용한 비휘발성 메모리 소자 제조방법에서, 상기 유전막 패턴을 형성하기 위하여 우선 기판 상에 하부 패턴들을 형성한다. 상기 하부 패턴들의 측벽 및 상부면과 기판 표면 상에 제1 유전막을 형성한다. 상기 제1 유전막 상에 마스크 패턴을 형성한다. 상기 마스크 패턴에 의해 노출된 상기 하부 패턴들 상부면 및 상부 측벽에 형성된 제1 유전막을 제거하고 상기 제거된 제1 유전막이 상기 하부 패턴들 사이에 위치한 제1 유전막 표면으로 재증착되도록 함으로써, 상기 기판 표면에서 상대적으로 두께가 더 두꺼운 제2 유전막을 형성한다. 다음에, 상기 하부 패턴들의 측벽 및 기판 상에 형성된 제2 유전막을 제거함으로써, 상기 마스크 패턴 아래에 유전막 패턴을 형성한다. 상기 방법에 의하면, 하부에 형성된 막의 손상을 감소시키고, 유전막 패턴 사이의 측벽 부위에 불필요한 유전막을 남기지 않을 수 있다.
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