公开(公告)号：KR1020090008607A

公开(公告)日：2009-01-22

申请号：KR1020070071680

申请日：2007-07-18

Applicant: 삼성전자주식회사

Inventor： 박규술 ,  강덕동

IPC: H01L21/28

CPC classification number: H01L21/76829 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: A method for forming a contact is provided to prevent contact failure due to an excessive etching process by controlling the etching thickness. A first interlayer insulating film including first contact pads(133) is formed on a semiconductor substrate(100). A second interlayer insulating film is formed on the first interlayer insulating film and reclaims a part of a bit line structure. An etch prevention film(155) is formed on the second interlayer insulating layer. A third interlayer insulating film(157) is formed on the etch prevention film and the bit line structure interval is reclaimed. First contact holes(163) are formed and an upper part of the etch prevention film is exposed by performing the etching process using the polysilicon pattern as the etching mask. The etching process is performed by using the expanded first contact holes. Second contact holes(165) are formed and the first contact pads are exposed. The second contact pads(169) for contacting a storage electrode are formed by reclaiming the first contact holes and the second contact holes.

Abstract translation: 提供一种用于形成接触的方法，以通过控制蚀刻厚度来防止由于过度的蚀刻工艺引起的接触故障。 包括第一接触焊盘（133）的第一层间绝缘膜形成在半导体衬底（100）上。 在第一层间绝缘膜上形成第二层间绝缘膜，并回收位线结构的一部分。 在第二层间绝缘层上形成防蚀膜（155）。 在防蚀膜上形成第三层间绝缘膜（157），并回收位线结构间隔。 通过使用多晶硅图案作为蚀刻掩模进行蚀刻处理，形成第一接触孔（163）并且防蚀膜的上部被暴露。 通过使用扩大的第一接触孔来进行蚀刻工艺。 形成第二接触孔（165），露出第一接触垫。 用于接触存储电极的第二接触焊盘（169）通过回收第一接触孔和第二接触孔而形成。

公开(公告)号：KR1020080005766A

公开(公告)日：2008-01-15

申请号：KR1020060064526

申请日：2006-07-10

Applicant: 삼성전자주식회사

Inventor： 박규술 ,  강덕동 ,  홍원철 ,  신상규 ,  김현창 ,  마종완

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L28/91

Abstract: A DRAM device and a manufacturing method thereof are provided to increase a capacitance of the DRAM device by enlarging a surface area of a lower electrode to be greater than that of a cylindrical lower electrode. A DRAM device includes interlayer dielectrics(17,21,31), a lower electrode contact(34a), a lower electrode(38), a dielectric film, and an upper electrode. The interlayer dielectrics are formed on a semiconductor substrate. The lower electrode contact is arranged to penetrate the interlayer dielectric to be electrically connected to the semiconductor substrate. The lower electrode contact includes a recessed region thereon. The lower electrode includes a fixed region, which is contacted with the lower electrode contact and arranged on the recessed region. The dielectric film and the upper electrode are formed on the lower electrode.

Abstract translation: 提供DRAM器件及其制造方法，通过将下电极的表面积扩大到比圆筒形下电极的表面积大，来增加DRAM器件的电容。 DRAM器件包括层间电介质（17,21,31），下电极接触（34a），下电极（38），电介质膜和上电极。 层间电介质形成在半导体衬底上。 下电极接触件布置成穿透层间电介质以电连接到半导体衬底。 下电极接触件包括其上的凹陷区域。 下电极包括固定区域，其与下电极接触件接触并且布置在凹陷区域上。 电介质膜和上电极形成在下电极上。

公开(公告)号：KR100699915B1

公开(公告)日：2007-03-28

申请号：KR1020060022970

申请日：2006-03-13

Applicant: 삼성전자주식회사

Inventor： 김현창 ,  신상규 ,  홍원철 ,  박규술 ,  마종완

IPC: H01L27/108 ,  H01L21/8242 ,  H01L21/28

CPC classification number: H01L27/10855 ,  H01L27/10885

Abstract: A semiconductor device and a method for manufacturing the same are provided to reduce the bridge between storage node contacts by forming an etch blocking pattern of bar shape. A first interlayer dielectric having contact pads(110a,110b) is formed on a substrate(100). Bit line structures are elongated to a first direction on the first interlayer dielectric. Insulating spacers are formed both sidewalls of the bit line structures. An etch blocking pattern of bar shape is formed between the bit line structures and elongated to a second direction. A second interlayer dielectric(122) is covered on the bit line structures. Storage node contacts(142) are formed between the bit line structures having the insulating spacer to connect the contact pad, wherein the upper part is wider than the lower part, and the upper part is contacted with the etch blocking pattern to the first direction and contacted with the insulating spacer to the second direction.

Abstract translation: 提供半导体器件及其制造方法，以通过形成条形蚀刻阻挡图案来减小存储节点触点之间的桥接。 在衬底（100）上形成具有接触焊盘（110a，110b）的第一层间电介质。 位线结构在第一层间电介质上延伸到第一方向。 绝缘垫片形成在位线结构的两个侧壁上。 在位线结构之间形成条形的蚀刻阻挡图案并且延伸到第二方向。 第二层间电介质（122）被覆盖在位线结构上。 存储节点触点（142）形成在具有绝缘间隔物的位线结构之间以连接接触焊盘，其中上部比下部更宽，并且上部与蚀刻阻挡图案接触第一方向，并且 与第二方向的绝缘垫片接触。

公开(公告)号：KR1020090011445A

公开(公告)日：2009-02-02

申请号：KR1020070075030

申请日：2007-07-26

Applicant: 삼성전자주식회사

Inventor： 박규술 ,  강덕동

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814

Abstract: A semiconductor device and manufacturing method thereof are provided to minimize the contact resistance by forming the storage electrode in the central part. The first interlayer insulating film including contact pads(110a,110b) is formed on the semiconductor substrate(100). Bit line structures extended to the first direction are formed on the first interlayer insulating film. The second inter metal dielectric(122) covering the bit line structures is formed. The upper contact hole contacting with the side wall of the bit line structures in zigzag shape is formed by etching partially the second interdielectric between bit line structures. The second inter metal dielectric positioned under the upper contact hole and the lower contact hole which partly etches the first interlayer insulating film and which compares with the upper contact hole and in which the inside width becomes narrow and exposing the upper side of the contact pad are formed. The storage node contacts(142) contact with the insulation spacer in all directions by burying the conductive material in the upper contact hole and lower contact hole. The capacitor(150) is formed in the upper side of the storage node contact.

Abstract translation: 提供半导体器件及其制造方法，以通过在中心部分形成存储电极来最小化接触电阻。 包括接触焊盘（110a，110b）的第一层间绝缘膜形成在半导体衬底（100）上。 在第一层间绝缘膜上形成延伸到第一方向的位线结构。 形成覆盖位线结构的第二金属间介电体（122）。 通过在位线结构之间部分地蚀刻第二介电质而形成以Z字形形状与位线结构的侧壁接触的上接触孔。 位于上接触孔下方的第二金属间电介质和下部接触孔，其部分地蚀刻第一层间绝缘膜，并且与上接触孔相比较，内宽度变窄并暴露接触焊盘的上侧， 形成。 存储节点触点（142）通过将导电材料埋入上接触孔和下接触孔中而在绝缘垫片的所有方向上接触。 电容器（150）形成在存储节点触点的上侧。

公开(公告)号：KR1020090012757A

公开(公告)日：2009-02-04

申请号：KR1020070076872

申请日：2007-07-31

Applicant: 삼성전자주식회사

Inventor： 마종완 ,  권준모 ,  박규술 ,  김현창 ,  정승욱 ,  김형준 ,  이윤경

IPC: H01L21/28

CPC classification number: H01L21/76802 ,  H01L21/31111 ,  H01L21/76825 ,  H01L27/10855

Abstract: A contact forming method of the semiconductor device is provided to expand the effective contact area between the storage node and the storage node contact on the semiconductor substrate provided regardless of the location of the source area or the drain region of transistor. A contact forming method of the semiconductor device comprises a step for forming insulating layers(124,132); a step for forming a mask(134); a step for forming an impurity region(138); a step for forming the contact hole; and a step for forming a contact. The insulating layer is formed on a substrate(100). Mask is formed on the insulating layer in order to partly expose the insulating layer. The impurity region is formed in the fixed region of the insulating layer through the mask. The contact hole is formed in the insulating layer in order to pass the impurity region.

Abstract translation: 提供了一种半导体器件的接触形成方法，用于扩展所提供的半导体衬底上的存储节点和存储节点接触之间的有效接触面积，而与晶体管的源极区域或漏极区域无关。 半导体器件的接触形成方法包括形成绝缘层（124,132）的步骤。 用于形成掩模的步骤（134）; 用于形成杂质区（138）的步骤; 形成接触孔的步骤; 以及形成接触的步骤。 绝缘层形成在基板（100）上。 掩模形成在绝缘层上，以便部分地暴露绝缘层。 通过掩模在绝缘层的固定区域中形成杂质区域。 为了通过杂质区域，在绝缘层中形成接触孔。

公开(公告)号：KR1020130005878A

公开(公告)日：2013-01-16

申请号：KR1020110067535

申请日：2011-07-07

Applicant: 삼성전자주식회사

Inventor： 박종현 ,  오재희 ,  박규술

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/1021 ,  H01L27/101 ,  H01L27/11507 ,  H01L27/224 ,  H01L27/2409 ,  H01L29/8613 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/146 ,  H01L29/45

Abstract: PURPOSE: A low resistive semiconductor device is provided to improve an operation property by maximizing a contact surface of a bottom electrode, an ohmic layer, and a pn junction diode to minimize contact resistance. CONSTITUTION: A first interlayer dielectric layer(107) with a cell contact hole(111) is formed on a word line(102). A pn junction diode(113) is located in the cell contact hole. An ohmic layer(115) to reduce ohmic contact resistance with a bottom electrode(119) is formed on the upper side of the pn junction diode. A storage device(121) is located on the upper side of the bottom electrode. A top electrode(123) and a bit line contact plug(127) are located on the upper side of the storage device.

Abstract translation: 目的：提供一种低电阻半导体器件，以通过使底部电极，欧姆层和pn结二极管的接触表面最大化来改善操作性能，以使接触电阻最小化。 构成：在字线（102）上形成具有单元接触孔（111）的第一层间介质层（107）。 pn结二极管（113）位于电池接触孔中。 在pn结二极管的上侧形成用于降低与底部电极（119）的欧姆接触电阻的欧姆层（115）。 存储装置（121）位于底部电极的上侧。 顶部电极（123）和位线接触插头（127）位于存储装置的上侧。

公开(公告)号：KR1020120104040A

公开(公告)日：2012-09-20

申请号：KR1020110022107

申请日：2011-03-11

Applicant: 삼성전자주식회사

Inventor： 박규술 ,  오재희 ,  주흥진

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/143

Abstract: PURPOSE: A phase change memory device and a manufacturing method thereof are provided to have an etch stop layer including a metal oxide layer which an etch selection ratio is higher than the ratio of a metal nitride layer of a lower portion electrode, thereby minimizing damage of the lower portion electrode, when a knoll structure is formed. CONSTITUTION: A mold oxide layer is formed on a substrate. A lower portion electrode(30) is formed on the mold oxide layer. The lower portion electrode is connected to the substrate. A knoll structure(40) covers a part of the lower portion electrode. The knoll structure includes an etch stop layer(42) and a knoll insulation layer. A phase change layer covers the rest of the lower portion electrode exposed from the knoll structure. The etch stop layer includes a material which is a high etch selection ratio for the lower portion electrode.

Abstract translation: 目的：提供一种相变存储器件及其制造方法，以具有包括金属氧化物层的蚀刻停止层，其蚀刻选择比高于下部电极的金属氮化物层的比例，从而最小化损伤 下部电极，当形成结构时。 构成：在基板上形成模具氧化物层。 在模具氧化物层上形成下部电极（30）。 下部电极与基板连接。 榫头结构（40）覆盖下部电极的一部分。 结构结构包括蚀刻停止层（42）和绝缘层。 相变层覆盖从knoll结构暴露的下部电极的其余部分。 蚀刻停止层包括对于下部电极是高蚀刻选择比的材料。

公开(公告)号：KR1020070109018A

公开(公告)日：2007-11-15

申请号：KR1020060041447

申请日：2006-05-09

Applicant: 삼성전자주식회사

Inventor： 신상규 ,  김현창 ,  홍원철 ,  박규술 ,  마종완

IPC: H01L21/768

CPC classification number: H01L23/544 ,  H01L21/7684 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A method for manufacturing a semiconductor device is provided to maintain a step between an alignment key pattern and an interlayer dielectric in a post process by protecting the alignment key pattern by using a protective layer. A substrate(100) including a chip area and a scribe line is prepared. A plurality of alignment key patterns(108) are formed on the scribe line of the substrate. An interlayer dielectric(110) is formed to fill a gap between the alignment key patterns. A protective layer is formed on the alignment key patterns and the interlayer dielectric. A circuit pattern(114) is formed on the chip area of the substrate. A lower pattern and a lower interlayer dielectric are formed on the chip area. The alignment key patterns are formed on the scribe line of the substrate while the lower pattern and the lower interlayer dielectric are formed on the chip area.

Abstract translation: 提供一种制造半导体器件的方法，通过使用保护层保护对准键图案，在后处理中保持对准键图案和层间电介质之间的台阶。 制备包括芯片区域和划线的衬底（100）。 多个对准键图案（108）形成在基板的划线上。 形成层间电介质（110）以填充对准键图案之间的间隙。 在对准键图案和层间电介质上形成保护层。 电路图案（114）形成在基板的芯片区域上。 在芯片区域上形成下图案和下层间电介质。 对准键图案形成在基板的划线上，而下图案和下层间电介质形成在芯片区域上。