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公开(公告)号：KR102237821B1
公开(公告)日：2021-04-08
申请号：KR1020140039362A
申请日：2014-04-02
Abstract: 하기 화학식 1로 표시되는 제1금속 산화물; 및 알칼리 토금속 산화물을 포함하는 금속산화물계 재료; 이를 포함하는 연료전지 및 이의 제조 방법을 개시한다.
Ce
(1.0-x) M
1
(x) O
(2-δ)
상기 화학식 1 중, M
1 , x 및 δ는 상세한 설명에 기재된 바와 같다.-
公开(公告)号：KR102237821B1
公开(公告)日：2021-04-08
申请号：KR1020140039362
申请日：2014-04-02
IPC: H01M8/126 , H01M8/1213 , H01M4/88 , H01M8/124
Abstract: 하기화학식 1로표시되는제1금속산화물; 및알칼리토금속산화물을포함하는금속산화물계재료; 이를포함하는연료전지및 이의제조방법을개시한다. Ce(1.0-x)M1(x)O(2-δ) 상기화학식 1 중, M1, x 및δ는상세한설명에기재된바와같다.
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公开(公告)号：KR1020150134984A
公开(公告)日：2015-12-02
申请号：KR1020140062572
申请日：2014-05-23
Applicant: 삼성전자주식회사
CPC classification number: H01B1/02 , C01B35/04 , C01P2006/40 , C01P2006/60 , G06F3/041 , H01B1/06 , H01L31/022466
Abstract: 층상구조를가지고 5족전이원소와붕소를포함하는화합물을포함하는투명도전체및 상기투명도전체를포함하는전자소자에관한것이다.
Abstract translation: 本发明涉及一种具有层结构并包含第5族过渡元素和硼的透明导体以及包括该透明导体的电子器件。 提供了具有柔性的透明导体，同时确保低电阻和高透明度。
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公开(公告)号：KR100840791B1
公开(公告)日：2008-06-23
申请号：KR1020020045392
申请日：2002-07-31
Applicant: 삼성전자주식회사
IPC: H01L21/8247
Abstract: 불휘발성 메모리 장치의 게이트 전극 형성 방법이 개시되어 있다. 반도체 기판 상에 터널 산화막, 제1도전층, 층간유전막 및 제2도전층을 순차적으로 형성한다. 상기 제2도전층 상에 게이트 영역을 정의하는 마스크 패턴을 형성한다. 상기 마스크 패턴과 면접되는 제2도전층 상면의 양측부를 제1식각함으로서, 상기 제2도전층에 리세스가 형성되도록 상기 마스크 패턴 하면의 양측부를 노출시킨다. 상기 하드 마스크 패턴을 식각 마스크로 이용하여 상기 리세스가 형성된 제2도전층을 제2식각함으로서 상기 마스크 패턴의 선폭보다 작은 컨트롤 게이트 패턴을 형성한다. 상기 결과물을 식각 마스크로 이용하여 상기 층간유전막 및 제1도전층을 제3식각하여 플로팅 게이트를 형성하는 단계를 갖는다. 상기 방법으로 형성된 게이트 전극은 플라즈마를 이용한 식각공정시 상기 플라즈마 이온으로 인해 손상을 방지할 수 있다.
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Patent Agency Ranking
公开(公告)号：KR1020040012041A
公开(公告)日：2004-02-11
申请号：KR1020020045393
申请日：2002-07-31
Applicant: 삼성전자주식회사
IPC: H01L21/3065
Abstract: PURPOSE: A method for fabricating a gate electrode of a non-volatile memory(NVM) device is provided to prevent a metal silicide layer pattern formed in the edge region of a semiconductor substrate from being physically and chemically damaged by using plasma ions in a gate electrode formation process. CONSTITUTION: A mask pattern for defining a gate region is formed on the semiconductor substrate(W) in which a tunnel oxide layer, the first conductive layer, an interlayer dielectric and the second conductive layer are sequentially stacked. The first etch process is performed on the second conductive layer to form a control gate pattern by using the mask pattern as an etch mask. The plasma etching apparatus includes a plasma shielding wall(150) for shielding plasma that causes damage to control gate pattern formed in the edge region(We) of the semiconductor substrate in a process for etching the interlayer dielectric and the second conductive layer. The second etch process is performed on the interlayer dielectric and the first conductive layer to form a floating gate pattern by using the plasma etching apparatus.
Abstract translation: 目的：提供一种用于制造非易失性存储器（NVM）器件的栅电极的方法，以防止在半导体衬底的边缘区域中形成的金属硅化物层图案通过在栅极中使用等离子体离子物理和化学损坏 电极形成过程。 构成：在隧道氧化物层，第一导电层，层间电介质和第二导电层依次堆叠的半导体衬底（W）上形成用于限定栅极区的掩模图案。 通过使用掩模图案作为蚀刻掩模，在第二导电层上执行第一蚀刻工艺以形成控制栅极图案。 等离子体蚀刻装置包括用于屏蔽等离子体的等离子体屏蔽壁（150），其在蚀刻层间电介质和第二导电层的工艺中对形成在半导体衬底的边缘区域（We）中的控制栅极图案造成损坏。 通过使用等离子体蚀刻装置，在层间电介质和第一导电层上进行第二蚀刻工艺以形成浮栅图案。
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公开(公告)号：KR1020030068324A
公开(公告)日：2003-08-21
申请号：KR1020020008218
申请日：2002-02-15
Applicant: 삼성전자주식회사
IPC: H01L21/3065
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of restraining long cone shaped particles from being generated at the peripheral portion of a wafer by using an etching apparatus having a predetermined clamp while forming an OSC structure capacitor on the wafer. CONSTITUTION: A wafer(W) is loaded in a chamber(10) for carrying out an etching process. At this time, a lower metal line and a poly layer are formed at the upper portion of the wafer. Plasma is generated in the chamber by flowing etching gas. Then, the poly layer is entirely etched by using the plasma. At this time, a clamp(25) is used for preventing the poly layer formed at the peripheral portion of the wafer from being etched. Preferably, the peripheral portion of the wafer is covered with the clamp as much as 0.7-1.3 mm. Preferably, the clamp is spaced apart from the peripheral portion of the wafer as much as 0.5-1 mm.
Abstract translation: 目的：提供一种制造半导体器件的方法，其能够通过使用具有预定夹具的蚀刻装置在晶片上形成OSC结构电容器来限制在晶片的周边部分处产生长锥形颗粒。 构成：将晶片（W）装载在用于进行蚀刻工艺的室（10）中。 此时，在晶片的上部形成下金属线和多晶硅层。 通过流动蚀刻气体在腔室中产生等离子体。 然后，通过使用等离子体完全蚀刻多层。 此时，使用夹具（25）来防止在晶片的周边部分形成的多晶硅层被蚀刻。 优选地，晶片的周边部分被夹具覆盖多达0.7-1.3mm。 优选地，夹具与晶片的周边部分间隔开多达0.5-1mm。
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公开(公告)号：KR1020010056698A
公开(公告)日：2001-07-04
申请号：KR1019990058275
申请日：1999-12-16
Applicant: 삼성전자주식회사
IPC: H01L21/3065
Abstract: PURPOSE: A method for processing plasma is provided to efficiently remove reaction by-products while minimizing generation of contaminant particles caused in a cleaning process during a plasma process. CONSTITUTION: A method for processing plasma etches a silicon film quality on a wafer within a reaction chamber using plasma generated from a halogen-group element-containing gas while supplying RF electric field to the reaction chamber. The interior of the reaction chamber is cleaned using plasma generated from gas containing O2 gas while reducing the power of the RF electric field applied to the reaction chamber by a given ramping rate.
Abstract translation: 目的：提供一种处理等离子体的方法，以有效地除去反应副产物，同时最小化在等离子体处理过程中清洗过程中产生的污染物颗粒。 构成：用于处理等离子体的方法利用从含卤素元素的气体产生的等离子体在反应室内的晶片上蚀刻硅膜质量，同时向反应室供应RF电场。 使用由含有O 2气体的气体产生的等离子体来清洁反应室的内部，同时以给定的斜坡率降低施加到反应室的RF电场的功率。
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公开(公告)号：KR1020000025668A
公开(公告)日：2000-05-06
申请号：KR1019980042828
申请日：1998-10-13
Applicant: 삼성전자주식회사
IPC: H01L21/66
Abstract: PURPOSE: A particle judgement method of an electrostatic chuck and a transcription effect judgement method of cleaning chemical processing are provided to estimate the type and the constituent of a particle attached on a backside of an electrostatic chuck as well as to estimate the process that the particle attached on the backside of the electrostatic chuck is removed in a succeeding processes and is transcribed from the backside of a wafer to the surface of other wafer. CONSTITUTION: Effect in a succeeding process like a cleaning process can be estimated by analyzing the type and the constituent of a particle remained on a backside of a wafer after loading/unloading by turning over a bare wafer or a wafer having a pattern and putting it into an electrostatic chuck in a process chamber. The type and the constituent of the particle remained on the backside of the wafer is analyzed with an energy dispersion analysis method using an in-line SEM(scanning electron microscope).
Abstract translation: 目的：提供一种静电卡盘的粒子判断方法和清洁化学处理的转录效果判断方法，以估计安装在静电卡盘背面的颗粒的类型和组成，并估计颗粒的过程 附着在静电卡盘的背面的部件在后续处理中被去除并且从晶片的背面转录到其它晶片的表面。 构成：可以通过分析在装载/卸载后残留在晶片背面的颗粒的类型和组成，通过翻转裸晶片或具有图案的晶片并将其放置，来估计在后续处理中的影响 进入处理室中的静电卡盘。 使用在线SEM（扫描电子显微镜）的能量分散分析方法分析残留在晶片背面的颗粒的种类和成分。
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公开(公告)号：KR1020160069364A
公开(公告)日：2016-06-16
申请号：KR1020140175234
申请日：2014-12-08
Applicant: 삼성전자주식회사
CPC classification number: H01L21/02186 , B32B5/16 , B32B15/04 , B32B2307/202 , B32B2307/704 , H01B1/02 , H01L21/02172 , H01L21/02197 , H01L27/016 , H01B1/08 , H01B5/00
Abstract: 하기화학식 1 로나타내어지고층상결정구조를가지는도핑된티타늄산화물을포함하는복수개의나노시트를포함하는전도성박막및 이를포함하는전자소자에대한것이다: [화학식 1] (ATi)O상기식에서, δ는 0 보다큰 수이고, A는 Nb, Ta, V, W, Cr, 및 Mo 로부터선택된적어도하나의도펀트금속을나타내며, α는 0 보다크고 1 보다작은수임.
Abstract translation: 本发明涉及一种具有高导电性和优异透光性的柔性的导电薄膜，以及包括该导电薄膜的电子器件。 导电薄膜包括多个纳米片，其具有由化学式1表示的具有层状晶体结构的掺杂二氧化钛。 化学式1：（A_αTi_（1-α））O_（2 +δ）其中化学式1中δ大于0; A是选自Nb，Ta，V，W，Cr和Mo中的至少一种掺杂剂金属; α大于0且小于1。
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