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Patent Agency Ranking
公开(公告)号：KR101855802B1
公开(公告)日：2018-05-10
申请号：KR1020110061483
申请日：2011-06-24
Applicant: 삼성전자주식회사
IPC: G01R31/28
CPC classification number: G01R31/318371
Abstract: 패턴합성기기및 이를포함하는반도체테스트시스템이개시된다. 본발명에따른반도체테스트시스템은가변적동작주파수를가지는타이밍신호에동기동기된인터페이스신호에따라피시험반도체를동작시키는사용자장치, 사용자장치로부터전송된타이밍신호의인접한에지사이의간격인인터벌을측정하고, 타이밍신호에따라인터페이스신호의논리값을추출하여테스트패턴데이터를생성하는패턴합성기기및테스트패턴데이터를전송받아측정된인터벌을기초로타이밍신호를구현하고, 상기구현된타이밍신호에동기되어상기논리값이추출되도록테스트구동신호를생성하고이를 DUT에인가하여 DUT의동작상태를판단하는테스트기기를포함한다. 따라서, 가변주파수동작에따른반도체소자의불량여부를판단할수 있어실장형테스트의확장및 더높은테스트커버리지의효과를얻을수 있다.
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公开(公告)号：KR1020130000758A
公开(公告)日：2013-01-03
申请号：KR1020110061483
申请日：2011-06-24
Applicant: 삼성전자주식회사
IPC: G01R31/28
CPC classification number: G01R31/318371
Abstract: PURPOSE: A pattern synthesizing device and a semiconductor test system including the same are provided to improve test coverage and extend a mount type test. CONSTITUTION: A pattern capture system(1000) includes a user device(100), an event generator(200), and a pattern synthesizing device(300). The user device operates a testee semiconductor according to an interface signal synchronized with a timing signal having a variable frequency. The pattern synthesizing device measures an interval between edges of the timing signal and generates test pattern data by extracting a logical value of the interface signal according to the timing signal. A test device implements the timing signal based on the interval measured with the test pattern data and is synchronized with the timing signal to extract the logical value. The test device generates a test operating signal and determines an operating state by applying the signal to a DUT(Device Under Test). [Reference numerals] (100) User device; (200) Event generator; (310) Pre-processing unit; (320) Interval time measuring unit; (330) Logic value capturing unit; (340) Control signal generator; (350) Event checking unit; (360) Communication interface
Abstract translation: 目的：提供一种图形合成装置和包括该图形合成装置的半导体测试系统以改善测试覆盖范围并扩展安装型测试。 构成：图案捕获系统（1000）包括用户装置（100），事件发生器（200）和模式合成装置（300）。 用户装置根据与具有可变频率的定时信号同步的接口信号来操作被测体半导体。 图案合成装置测量定时信号的边缘之间的间隔，并通过根据定时信号提取接口信号的逻辑值来生成测试图案数据。 测试装置基于用测试图案数据测量的间隔实现定时信号，并与定时信号同步以提取逻辑值。 测试装置产生测试操作信号，并通过将信号施加到DUT（被测设备）来确定操作状态。 （附图标记）（100）用户装置; （200）事件发生器; （310）预处理单元; （320）间隔时间测量单位; （330）逻辑值捕获单元; （340）控制信号发生器; （350）事件检查单位; （360）通讯接口
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公开(公告)号：KR1020150040617A
公开(公告)日：2015-04-15
申请号：KR1020130119364
申请日：2013-10-07
Applicant: 삼성전자주식회사
IPC: G11C29/10
CPC classification number: G11C29/56004
Abstract: 본발명의일 실시예에따르면, 메모리장치를테스트하기위한메모리테스트장치에있어서, 서로다른제1 패턴메모리주소및 제2 패턴메모리주소를출력하는시퀀서, 상기제1 패턴메모리주소에따라제1 테스트패턴을출력하는제1 패턴생성기, 상기제2 패턴메모리주소에따라제2 테스트패턴을출력하는제2 패턴생성기, 및상기제1 테스트패턴및 상기제2 테스트패턴에따라기입데이터를생성하고출력하는기입데이터생성부를포함하는메모리테스트장치가제공된다.
Abstract translation: 根据本发明的实施例，一种用于测试存储器测试装置的存储器测试装置，包括：定序器，其输出彼此不同的第一模式存储器地址和第二模式存储器地址; 第一图案生成器，其根据第一图案存储器地址输出第一测试图案; 第二图案生成器，其根据第二图案存储器地址输出第二测试图案; 以及记录数据生成单元，其根据第一测试图案和第二测试图案生成并输出记录数据。
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