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公开(公告)号：KR1020100067487A
公开(公告)日：2010-06-21
申请号：KR1020080126070
申请日：2008-12-11
Applicant: 삼성전자주식회사
IPC: G01R31/3183 , G01R31/00 , H04B10/25 , G11C29/56
CPC classification number: G11C29/56 , G11C29/32 , G11C2029/2602 , G11C2029/5602
Abstract: PURPOSE: A test interface device, a test system, and an optical interface memory device are provided to reduce the use of an optical resource using serialization and paralleling technology. CONSTITUTION: A first serializing unit(131) receives a parallel test signal from an automatic test device and serializes a parallel test signal into a serial test signal. A first optical transmitter(133) receives a serial test signal from the first serializing unit, converts the serial test signal into an optical test signal, and transmits the optical test signal. A first optical receiver(134) receives the optical test signal and converts the optical test signal into the serial test signal. A first paralleling unit receives the serial test signal from the first optical receiver, converts the serial test signal into the parallel test signal, and transmits the parallel test signal to a test target device.
Abstract translation: 目的：提供测试接口设备，测试系统和光学接口存储设备，以减少使用串行化和并行技术的光学资源的使用。 构成：第一串行化单元（131）从自动测试装置接收并行测试信号，并行串行测试信号为串行测试信号。 第一光发射机（133）从第一串行化单元接收串行测试信号，将串行测试信号转换为光测试信号，并发送光测试信号。 第一光接收器（134）接收光测试信号并将光测试信号转换成串行测试信号。 第一并联单元从第一光接收器接收串行测试信号，将串行测试信号转换成并行测试信号，并将并行测试信号发送到测试对象设备。
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2.发明公开
公开(公告)号：KR1020100015206A
公开(公告)日：2010-02-12
申请号：KR1020080076148
申请日：2008-08-04
Applicant: 삼성전자주식회사
IPC: G01R31/302 , G01R1/06 , G01R31/26 , H01L21/66
CPC classification number: G01R31/2889 , G01R31/3025 , G01R31/303 , H01L2224/48472 , H01L2924/3011 , H01L2924/00
Abstract: PURPOSE: An interface device for wireless test, semiconductor device and package are provided to connect interface transmitter-receiver circuits and ensure stable function. CONSTITUTION: An interface antennas are formed on an interface substrate(14). Interface transmitter-receiver circuits(16) are formed on the interface substrate. The Interface transmitter-receiver circuits are connected through interface vias(18v) which penetrates input/output pads(15) and interface substrate. The interface substrate comprises PCB substrate, plastic substrate, glass substrate, and ceramic substrate.
Abstract translation: 目的：提供用于无线测试的接口设备，半导体器件和封装，以连接接收器发射机和接收机电路，确保稳定的功能。 构成：接口天线形成在接口基板（14）上。 接口发射机 - 接收机电路（16）形成在接口基板上。 接口发射机 - 接收机电路通过穿透输入/输出焊盘（15）和接口基板的接口通孔（18v）连接。 界面基板包括PCB基板，塑料基板，玻璃基板和陶瓷基板。
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公开(公告)号：KR1020100085390A
公开(公告)日：2010-07-29
申请号：KR1020090004645
申请日：2009-01-20
Applicant: 삼성전자주식회사
IPC: G01R31/3183 , G01R31/3177 , G01R31/26 , H01L21/66
CPC classification number: G01R31/31932 , G11C29/56 , G11C29/56012 , G11C2029/5602
Abstract: PURPOSE: A semiconductor device test apparatus and a semiconductor device test method are provided to determine the bad quality of a semiconductor device of an object by improving the operating speed of the semiconductor device of an object. CONSTITUTION: An object(300) positions a semiconductor device to be inspected. Automatic test equipment(100) inputs test signals to the object and analyzes test result signals. An interface unit(200) is interposed between the object and the auto test equipment, compares test signals with test result signals, and outputs test determination signals to the auto test equipment.
Abstract translation: 目的：提供半导体器件测试装置和半导体器件测试方法，以通过提高对象的半导体器件的操作速度来确定对象的半导体器件的质量差。 构成：物体（300）定位待检查的半导体器件。 自动测试设备（100）向测试对象输入测试信号并分析测试结果信号。 接口单元（200）介于物体与自动测试设备之间，将测试信号与测试结果信号进行比较，并向自动测试设备输出测试确定信号。
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公开(公告)号：KR1020060104392A
公开(公告)日：2006-10-09
申请号：KR1020050026525
申请日：2005-03-30
Applicant: 삼성전자주식회사
IPC: G01R31/28
CPC classification number: G01R31/31924 , G01R1/0433 , G01R1/07307
Abstract: 본 발명에 따른 반도체 디바이스 테스트 장치는 입력 전송 라인과 출력 전송 라인간을 접속 또는 차단하거나 입력 전송 라인과 비교기의 연결을 유지한 상태로 입력 전송 라인과 반도체 디바이스간을 접속 또는 차단하는 스위칭부를 구비한다. 이에 의하면 단일 전송 라인 구성과 이중 전송 라인 구성 변경이 가능하므로 임피던스 특성이 다른 두 종류의 반도체 디바이스에 대한 임피던스 매칭이 가능하여 정확한 테스트 결과를 얻을 수 있다.
STL, DTL, 소켓, 프로브 카드, 테스트-
公开(公告)号：KR101535228B1
公开(公告)日：2015-07-08
申请号：KR1020090041749
申请日：2009-05-13
Applicant: 삼성전자주식회사
IPC: G01R31/3183 , G01R31/26 , H01L21/66
CPC classification number: G01R31/2831 , G01R31/31915 , G01R31/31922 , G11C29/56
Abstract: 본발명은반도체장치의테스트를위하여반도체장치와외부테스트장치사이에결합되는빌트오프테스트장치에관한것이다. 본발명의일 실시예에따른빌트오프테스트장치는, 반도체장치와상기반도체장치를테스트하기위한외부테스트장치사이에결합되는빌트오프테스트장치로서, 상기빌트오프테스트장치는, 상기반도체장치의동작속도에기초하여, 상기외부테스트장치로부터입력되는클럭주파수를채배하여, 테스트클럭주파수를생성하는주파수채배부; 상기테스트클럭주파수를기초로상기외부테스트장치로부터입력되는테스트신호를디코딩하여테스트정보를생성하는명령디코더부; 및상기테스트정보에따라상기반도체장치에대한테스트를수행하고, 상기반도체장치로부터출력된테스트데이터로부터상기반도체장치의불량여부를판정하여, 판정데이터를상기외부테스트장치에전달하는테스트실행부를포함할수 있다.
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Patent Agency Ranking
公开(公告)号：KR1020060040066A
公开(公告)日：2006-05-10
申请号：KR1020040089256
申请日：2004-11-04
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01R1/07307 , G01R31/2601
Abstract: 본 발명의 니들컨택장치는, 반도체웨이퍼 테스트를 위하여 반도체웨이퍼의 다이패드들에 대응되는 니들들을 구비하는 프루브카드의 캘리브레이션을 위한 니들컨택장치이다. 이 니들컨택장치는, 절연성 바디와, 이 절연성 바디의 상부면에 배치되되 프루브카드의 니들들의 위치에 대응되는 위치에 배치되는 복수개의 패드들과, 그리고 절연성 바디의 일 측면에서 복수개의 패드들의 각각에 연결되는 복수개의 단자들을 구비한다.
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公开(公告)号：KR101511161B1
公开(公告)日：2015-04-13
申请号：KR1020090004645
申请日：2009-01-20
Applicant: 삼성전자주식회사
IPC: G01R31/3183 , G01R31/3177 , G01R31/26 , H01L21/66
CPC classification number: G01R31/31932 , G11C29/56 , G11C29/56012 , G11C2029/5602
Abstract: 본발명의반도체소자검사장치는제1 주파수의테스트신호를주파수체배부에입력하는자동테스트설비부와, 상기주파수체배부에서주파수가체배되어제2 주파수의테스트신호가입력되고반도체소자가위치하는피검사부와, 상기피검사부의상기반도체소자에서출력되는제2 주파수의테스트결과신호와상기주파수체배부를통해제2 주파수의테스트신호가입력되고, 상기테스트결과신호와상기테스트신호를비교하여상기제1 주파수로고 레벨및 저레벨의테스트판정신호를출력하는제1 비교기와, 상기피검사부의반도체소자에서출력되는제2 주파수의테스트결과신호와상기주파수체배부를통해제2 주파수의테스트신호가입력되고, 위상선택기를포함하여상기테스트결과신호와상기테스트신호간의위상을비교하여상기제1 주파수의테스트판정신호를출력하는제2 비교기와, 및상기자동테스트설비부로부터의선택신호에따라상기제1 비교기및 제2 비교기중어느하나를선택하는선택기를포함한다.
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公开(公告)号：KR1020130022622A
公开(公告)日：2013-03-07
申请号：KR1020110085337
申请日：2011-08-25
Applicant: 삼성전자주식회사
IPC: H01L21/677 , H01L21/50 , B65G49/07
CPC classification number: H01L21/67132 , H01L21/67144 , H01L21/67721 , H01L21/67754 , H01L21/6838
Abstract: PURPOSE: A conductor chip pickup device is provided to reduce manufacturing time and costs by simultaneously transferring a plurality of semiconductor chips. CONSTITUTION: A first top transfer driving unit(100a) and a second top transfer driving unit(100b) are separated in parallel in an X axis direction. A top guide rail is installed between the first top transfer driving unit and the second top transfer driving unit. A plurality of pickers(500a,500b) are combined with the top guide rail. A first bottom transfer driving unit(200a) and a second bottom transfer driving unit(200b) are separated in the X axis direction. A bottom guide rail is installed between the first bottom transfer driving unit and the second bottom transfer driving unit. A plurality of plungers(600a,600b) are combined with the bottom guide rail.
Abstract translation: 目的：提供一种导体芯片拾取装置，通过同时传送多个半导体芯片来减少制造时间和成本。 构成：第一顶部传送驱动单元（100a）和第二顶部传送驱动单元（100b）在X轴方向上平行分离。 顶部导轨安装在第一顶部传送驱动单元和第二顶部传送驱动单元之间。 多个拾取器（500a，500b）与顶部导轨结合。 第一底部传送驱动单元（200a）和第二底部传送驱动单元（200b）在X轴方向上分离。 底部导轨安装在第一底部传送驱动单元和第二底部传送驱动单元之间。 多个柱塞（600a，600b）与底部导轨结合。
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公开(公告)号：KR1020120138517A
公开(公告)日：2012-12-26
申请号：KR1020110058050
申请日：2011-06-15
Applicant: 삼성전자주식회사
CPC classification number: G01R31/2893 , H01L24/75 , H01L24/94 , H01L25/50 , H01L2224/16145 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A chip fixing apparatus and a chip testing method thereof are provided to improve the efficiency of operation process. CONSTITUTION: A chip fixing apparatus includes a chip tray(100) and a support chuck(200). The chip tray defines multiple field regions(110) on the surface and contains a first internal vacuum line(120). The support chuck contains a second internal vacuum line(220) and supports the chip tray.
Abstract translation: 目的：提供一种芯片定影装置及其芯片测试方法，以提高操作过程的效率。 构成：芯片定影装置包括芯片托盘（100）和支撑卡盘（200）。 芯片托盘在表面上限定多个场区域（110）并且包含第一内部真空管线（120）。 支撑卡盘包含第二内部真空管线（220）并支撑芯片托盘。
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公开(公告)号：KR1020100122719A
公开(公告)日：2010-11-23
申请号：KR1020090041749
申请日：2009-05-13
Applicant: 삼성전자주식회사
IPC: G01R31/3183 , G01R31/26 , H01L21/66
CPC classification number: G01R31/2831 , G01R31/31915 , G01R31/31922 , G11C29/56
Abstract: PURPOSE: A built-off test device is provided to test a semiconductor device which is rapidly operated. CONSTITUTION: A frequency multiplying part(310) generates a test clock frequency by multiplying a clock frequency which is inputted from an external test device based on the operation speed of a semiconductor device. A command decoder(320) generates test information by decoding a test signal which is inputted from the external test device based on a test clock frequency. A test executing part(330) determines whether the semiconductor device is in an abnormal state from the test data outputted from the semiconductor device.
Abstract translation: 目的：提供一种内置测试装置来测试快速操作的半导体器件。 构成：乘法部分（310）根据半导体器件的运行速度乘以从外部测试装置输入的时钟频率来产生测试时钟频率。 命令解码器（320）通过根据测试时钟频率对从外部测试设备输入的测试信号进行解码来产生测试信息。 测试执行部分（330）根据从半导体器件输出的测试数据确定半导体器件是否处于异常状态。
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