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公开(公告)号：KR101548674B1
公开(公告)日：2015-09-01
申请号：KR1020090079243
申请日：2009-08-26
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11575 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L2924/00
Abstract: 3차원반도체메모리장치및 그제조방법이제공된다. 3차원반도체메모리장치는서로이격된제 1 콘택영역및 제 2 콘택영역을포함하는기판및 차례로적층된복수의도전패턴들을포함하되, 도전패턴들각각은, 기판의상부면에평행한배선부및 기판의상부면을관통하는방향을따라, 배선부의일단으로부터연장되는콘택연장부를포함하고, 도전패턴들중의적어도하나의콘택연장부는제 1 콘택영역에배치되고, 상기도전라인들중 적어도다른하나의콘택연장부는제 2 콘택영역에배치된다.
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公开(公告)号：KR101265700B1
公开(公告)日：2013-05-20
申请号：KR1020080110364
申请日：2008-11-07
Applicant: 삼성전자주식회사
CPC classification number: G11C7/08 , G11C5/025 , G11C7/1012 , G11C7/12 , G11C2207/002
Abstract: 본발명은반도체메모리장치를공개한다. 이장치는워드라인들과상기워드라인과직교하는방향으로배치된비트라인들각각의사이에연결된메모리셀들을구비하는서브메모리셀 어레이영역, 상기서브메모리셀 어레이영역의상기워드라인방향의일측에배치되고, 상기워드라인들을구동하는서브워드라인드라이버를구비하는서브워드라인드라이브영역, 상기서브메모리셀 어레이영역의상기비트라인방향의일측에배치되고, 구동신호라인으로전송되는신호에응답하여상기비트라인을프리차지하는이퀄라이저, 및제어신호라인으로전송되는신호에응답하여반전제어신호라인을구동하는적어도하나의제1 제어신호드라이버를구비하는센싱영역, 및상기서브워드라인드라이브영역과상기센싱영역의교차점에배치되고, 상기반전제어신호라인과상기구동신호라인이연결되는접합영역을구비하는것을특징으로한다.
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公开(公告)号：KR1020090039341A
公开(公告)日：2009-04-22
申请号：KR1020070104922
申请日：2007-10-18
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01R31/2889 , H01R12/714
Abstract: An interposer and a probe card having the same for preventing interference which is electrical between signal lines within a base by arranging ground lines surrounding the signal line are provided to reduce the loss of the inspection current of the signal lines. An interposer(100) comprises a base(110), a signal line(120) and a ground line(130). The base has the signal lines and ground lines. Signal lines are exposed through the upper side and lower surface of the base. The signal current is provided each of the signal lines to the semiconductor structure. Ground lines are exposed through the upper side and lower surface of the base. The probe card comprises the multilayer board, a coaxial board and an interposer. The coaxial board has coaxial signal cables and coaxial ground cables. Coaxial signal cables electrically connect with the signal lines of interposer. Coaxial ground cables electrically connect with the ground lines of interposer.
Abstract translation: 为了减少信号线的检查电流的损失，提供了一种具有防止干扰的插入件和探针卡，用于通过布置围绕信号线的接地线来在基座内的信号线之间电气化。 插入器（100）包括基座（110），信号线（120）和接地线（130）。 基座有信号线和接地线。 信号线通过底座的上侧和下表面露出。 信号电流被提供给半导体结构的每条信号线。 接地线通过基座的上侧和下表面露出。 探针卡包括多层板，同轴板和插入件。 同轴板具有同轴信号电缆和同轴接地电缆。 同轴信号电缆与插入器的信号线电连接。 同轴接地电缆与插入器的接地线电连接。
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公开(公告)号：KR100891328B1
公开(公告)日：2009-03-31
申请号：KR1020070001183
申请日：2007-01-04
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01R31/2886 , G01R31/2889
Abstract: 본 발명은 병렬 테스트가 가능한 반도체 집적회로 테스트 시스템 및 반도체 집적회로 테스트 방법에 관한 것이다. 본 발명의 일실시예에 따른 병렬 타입 반도체 집적회로 테스트 시스템은, 서로 다른 종류를 갖는 복수의 DUT를 탑재하는 프로브 척; 상기 서로 다른 종류의 DUT들을 동시에 독립적으로 테스트하기 위한 복수의 회로 사이트를 제공하는 테스트 헤드; 및 상기 테스트 헤드 및 상기 프로브 척을 제어하는 테스트 제어부를 포함한다.
메모리 테스터, 다중 DUT, 플래시 메모리-
公开(公告)号：KR1020080064250A
公开(公告)日：2008-07-09
申请号：KR1020070000933
申请日：2007-01-04
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01R31/2851 , G01R1/04 , H05K1/144 , H05K1/148 , H05K2201/042 , H05K2201/09972 , H05K2201/10371
Abstract: A stacked test board for high-precision inspection is provided to enhance safety and reliability of inspection by minimizing or shielding the effect of electrical signals using a signal shield fence. A stacked test board for high-precision inspection includes plural test boards(10), spacers(20), connection cables(30), and signal shield fences(40). The test boards include plural mounting components mounted on a side thereof and input/output signal terminals at the end portions thereof. The spacers are used for arranging constantly the test boards by separating the test boards. The connection cables are positioned between the input/output signal terminals. The signal shield fences are formed up to constant height so as to prevent interference of electrical signals between mounting components on the test boards.
Abstract translation: 提供了一种用于高精度检测的堆叠测试板，通过使用信号屏蔽栅极最小化或屏蔽电信号的影响来提高检查的安全性和可靠性。 用于高精度检查的堆叠测试板包括多个测试板（10），间隔件（20），连接电缆（30）和信号屏蔽栅栏（40）。 测试板包括安装在其一侧的多个安装部件和其端部处的输入/输出信号端子。 间隔件用于通过分离测试板来不断地布置测试板。 连接电缆位于输入/输出信号端子之间。 信号屏蔽栅栏形成为恒定的高度，以防止电气信号在测试板上的安装部件之间的干扰。
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Patent Agency Ranking
公开(公告)号：KR1020080044440A
公开(公告)日：2008-05-21
申请号：KR1020060113299
申请日：2006-11-16
Applicant: 삼성전자주식회사
IPC: H01L27/146
CPC classification number: H01L27/1461 , H01L27/14607 , H01L27/14689
Abstract: An image sensor and a method for manufacturing the same are provided to improve the reliability of the image sensor by improving a field shift characteristic. An image sensor includes a semiconductor substrate(101), a photoelectric converter(110), and a charge transfer unit(130). The photoelectric converter is formed on the semiconductor substrate. The photoelectric converter includes a first photo diode(112) storing charge and a second photo diode(114) formed to overlap with a part or all of the first photo diode. The charge transfer unit transfers the charge stored in the photoelectric converter to a charge detector. A formation depth of the second photo diode is less than that of the first photo diode. A part of the second photo diode overlaps with the charge transfer unit.
Abstract translation: 提供了一种图像传感器及其制造方法，通过提高场偏移特性来提高图像传感器的可靠性。 图像传感器包括半导体衬底（101），光电转换器（110）和电荷转移单元（130）。 光电转换器形成在半导体衬底上。 光电转换器包括存储电荷的第一光电二极管（112）和形成为与第一光电二极管的一部分或全部重叠的第二光电二极管（114）。 电荷转移单元将存储在光电转换器中的电荷传送到电荷检测器。 第二光电二极管的形成深度小于第一光电二极管的形成深度。 第二光电二极管的一部分与电荷转移单元重叠。
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公开(公告)号：KR100791000B1
公开(公告)日：2008-01-03
申请号：KR1020060106718
申请日：2006-10-31
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01R31/2889
Abstract: An electrical test apparatus for testing a wafer at a high speed and a testing method thereof are provided to secure a high-speed test of GHz and more by simplifying a structure of a probe card and improving a connecting state between a probe card and a performance board. A test head(110) of a tester is used for inspecting a wafer. One side of a performance board(120) is connected to the test head. Connection parts of first coaxial cable are formed at the other side of the performance board in order to connect a signal line. A probe card(150) is connected to the performance board. Connection parts of second coaxial cable(154) are installed at a connecting surface of the probe card. A needle(156) for contacting the wafer is formed at the opposite surface of the probe card. A coaxial cable bundle(130) is formed to connect the first coaxial cable connecting parts of the performance board with the second coaxial cable connecting parts of the probe card.
Abstract translation: 提供一种用于高速测试晶片的电气测试装置及其测试方法，通过简化探针卡的结构并提高探针卡与性能之间的连接状态，确保了GHz及更高的高速测试 板。 测试器的测试头（110）用于检查晶片。 性能板（120）的一侧连接到测试头。 第一同轴电缆的连接部分形成在性能板的另一侧，以连接信号线。 探针卡（150）连接到演奏板。 第二同轴电缆（154）的连接部分安装在探针卡的连接表面。 用于接触晶片的针（156）形成在探针卡的相对表面。 形成同轴电缆束（130）以将性能板的第一同轴电缆连接部分与探针卡的第二同轴电缆连接部分连接起来。
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公开(公告)号：KR100613169B1
公开(公告)日：2006-08-17
申请号：KR1020040081308
申请日：2004-10-12
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01R31/307
Abstract: 본 발명은 무접촉 방식으로 반도체 소자의 특성을 테스트할 수 있는 무접촉 반도체 소자 테스트 장치를 제공한다. 즉, 테스트될 반도체 소자에 테스트 신호를 입력하는 테스트 신호 입력부와; 입력 전자빔을 발생시켜 입력된 상기 테스트 신호에 대한 출력 신호가 출력되는 상기 반도체 소자의 영역에 입력 전자빔을 조사하는 전자빔 조사기와; 조사된 상기 입력 전자빔에 의해 상기 반도체 소자에서 방출되는 출력 전자빔을 검출하는 검출기와; 입력된 상기 테스트 신호에 대응하여 상기 반도체 소자의 정상적인 동작을 할 때의 출력 파형과 상기 검출기에서 검출된 상기 출력 전자빔의 파형을 비교하여 상기 반도체 소자의 양불량을 판정하는 판별부;를 포함하는 것을 특징으로 하는 무접촉 반도체 소자 테스트 장치를 제공한다.
무접촉, 반도체 소자, 테스트, 전자빔, 회전-
公开(公告)号：KR1020100052959A
公开(公告)日：2010-05-20
申请号：KR1020080111874
申请日：2008-11-11
Applicant: 삼성전자주식회사
IPC: G01R1/073
CPC classification number: G01R31/2889 , G01R1/07378
Abstract: PURPOSE: The interface structure of a wafer inspection apparatus is provided to obtain the transmission property of a general signal line during a wafer inspection process by reducing the weight and the size of the probe card. CONSTITUTION: A performance board(300) is connected to a test head. An universal block printed circuit board(400) is directly connected with a general signal line and divides a power signal line in numbers. A probe card(100) installs a ceramic multi-layered substrate on the lower side of an interposer. Probes are arranged on the ceramic multi-layered substrate.
Abstract translation: 目的：提供晶片检查装置的接口结构，通过减小探针卡的重量和尺寸，在晶片检查过程中获得通用信号线的传输特性。 构成：性能板（300）连接到测试头。 通用块印刷电路板（400）与通用信号线直接连接，并分割数字的电源信号线。 探针卡（100）在中介层的下侧安装陶瓷多层基板。 探针布置在陶瓷多层基板上。
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公开(公告)号：KR1020080084467A
公开(公告)日：2008-09-19
申请号：KR1020070026256
申请日：2007-03-16
Applicant: 삼성전자주식회사
IPC: H01L21/66
Abstract: A test apparatus for a wafer chip stack and a method of testing the same are provided to test defects of the wafer chip stack loaded on a strip by employing a strip conveyor unit, a strip rail unit, a first NG vision unit, a strip aligning unit, a test contact unit, an NG marking unit, a second NG vision unit, and a strip discharge unit. A test apparatus for a wafer chip stack comprises a strip conveyor unit(10), a strip rail unit(20), a first NG vision unit(30), a strip aligning unit(40), a test contact unit(50), an NG marking unit(60), a second NG vision unit(70), and a strip discharge unit(80). The strip conveyor unit conveys a strip(1) on which wafer chip stacks are mounted. The strip rail unit connects with the strip conveyor unit and conveys the strip. The first NG vision unit is located on the strip rail unit, close to the strip conveyor unit to inspect NG marks on the wafer chip stack. The strip aligning unit is located in opposite side of the strip conveyor unit and arranges strips on the strip rail for the test. The test contact unit is located on the strip aligning unit, in the opposite side of the first NG vision unit and connects with the wafer chip stack electrically to perform the test. The NG marking unit is located between the test contact unit and the second NG vision unit and marks NG on the wafer chip stack with defects. The second NG vision unit is located between the NG marking unit and the strip discharge unit and inspects the state of the NG mark. The strip discharge unit is located at the end of the strip rail unit and discharges the strip subjected to the test and the NG marking process to the outside.
Abstract translation: 提供了一种用于晶片芯片堆叠的测试装置及其测试方法，用于通过使用带式输送机单元，带状轨道单元，第一NG视觉单元，条带对准件来测试加载在条带上的晶片芯片堆叠的缺陷 单元，测试接触单元，NG标记单元，第二NG视觉单元和带状排出单元。 一种用于晶片芯片堆叠的测试装置，包括一个带状输送单元（10），一个带状轨道单元（20），一个第一NG视觉单元（30），一个钢带对准单元（40），一个测试接触单元（50） NG标记单元（60），第二NG视觉单元（70）和带式排出单元（80）。 带式输送机单元输送其上安装有晶片芯片堆叠的条带（1）。 带状导轨单元与带状输送单元连接并传送带。 第一个NG视觉单元位于带状轨道单元上，靠近带状输送单元，以检查晶片芯片堆叠上的NG标记。 带材对齐单元位于带式输送机单元的相对侧，并将条带布置在带状轨上用于测试。 测试接触单元位于第一NG视觉单元的相对侧的带对齐单元上，并与晶片芯片电路电连接以进行测试。 NG标记单元位于测试接触单元和第二NG视觉单元之间，并且在晶片芯片堆叠上存在缺陷的NG。 第二个NG视觉单元位于NG标记单元和排纸单元之间，并检查NG标志的状态。 带状排放单元位于带状轨道单元的端部，并将经受测试的条带和NG标记过程排出到外部。
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