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公开(公告)号：KR1020130128989A
公开(公告)日：2013-11-27
申请号：KR1020120053253
申请日：2012-05-18
Applicant: 삼성전자주식회사
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0009 , G11C13/0069 , G11C2213/72
Abstract: A variable resistance non-volatile memory device includes a variable resistance memory cell array and an input/output circuit for inputting writing data from the outside or outputting reading data. The memory device includes an encoder for generating the writing data as DC balance code data and a writing circuit for writing the DC balance code data to the memory cell array. The memory device includes a sensing circuit for sensing the stored data from the memory cell array and a decoder for recovering the reading data offered to the input/output circuit by decoding the DC balance code data. The sensing circuit compares the average current of cell lead currents with each cell lead current. When the average current is bigger than a cell lead current, the sensing circuit senses a reset state. When the average current is smaller than the cell lead current, the sensing circuit senses a set state. The present invention reduces the impact of changes in cell resistance, which is generated by time, by using the average current of a DC balance state.
Abstract translation: 可变电阻非易失性存储器件包括可变电阻存储单元阵列和用于从外部输入写入数据或输出读取数据的输入/输出电路。 存储装置包括用于产生作为DC平衡码数据的写入数据的编码器和用于将DC平衡码数据写入存储单元阵列的写入电路。 存储器件包括用于感测来自存储单元阵列的存储数据的感测电路和用于通过解码DC平衡码数据来恢复提供给输入/输出电路的读取数据的解码器。 感测电路将电池引线电流的平均电流与每个电池引线电流进行比较。 当平均电流大于单元引线电流时，感测电路检测复位状态。 当平均电流小于单元引线电流时，感测电路感测设定状态。 本发明通过使用DC平衡状态的平均电流来减少由时间产生的电池电阻变化的影响。
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Patent Agency Ranking
公开(公告)号：KR101866293B1
公开(公告)日：2018-06-14
申请号：KR1020110084137
申请日：2011-08-23
Applicant: 삼성전자주식회사
CPC classification number: G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/0076 , G11C2013/0092
Abstract: 가변저항메모리장치의라이트신호생성회로가제공된다. 라이트신호생성회로는상기기술적과제를달성하기위한본 발명의일 실시예에따른라이트신호생성회로는, 프로그램대상메모리셀의위치정보를제공받고, 프로그램대상메모리셀의위치정보에따른프리-엠퍼시스신호를생성하는프리-엠퍼시스신호생성회로, 및프로그램대상메모리셀에프로그램될데이터에해당하는프로그램신호를생성하고, 이를프리-엠퍼시스신호생성회로로부터제공받은프리-엠퍼시스신호와합하여라이트신호를생성하고, 라이트신호를프로그램대상메모리셀로출력하는라이트드라이버를포함한다.
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公开(公告)号：KR101736383B1
公开(公告)日：2017-05-30
申请号：KR1020100074894
申请日：2010-08-03
Applicant: 삼성전자주식회사
CPC classification number: G11C7/12 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/004
Abstract: 메모리장치의글로벌비트라인프리차지방법이개시된다. 상기방법은메모리셀 어레이에포함된복수의서브어레이들사이에위치한적어도하나의제1프리차지회로를이용하여선택된글로벌비트라인을제1프리차지전압으로프리차지하는단계와, 상기메모리셀 어레이의외부위치하는제2프리차지회로를이용하여상기선택된글로벌비트라인을제2프리차지전압으로프리차지하는단계를포함한다.
Abstract translation: 公开了一种存储器件的全局位线预充电方法。 该方法包括使用位于存储器单元阵列中包括的多个子阵列之间的至少一个第一预充电电路将选定的全局位线预充电到第一预充电电压， 并且使用位于第二预充电电路的第二预充电电路将选定的全局位线预充电至第二预充电电压。
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公开(公告)号：KR1020130093298A
公开(公告)日：2013-08-22
申请号：KR1020120014762
申请日：2012-02-14
Applicant: 삼성전자주식회사
CPC classification number: G11C13/0002 , G11C13/0026 , G11C13/0061 , G11C13/0069 , G11C2013/0078 , G11C2213/72 , G11C2213/79
Abstract: PURPOSE: A resistive memory device, an operating method thereof, and a memory system including the same improve the distribution of a memory cell by blocking current flowing through the memory cell. CONSTITUTION: A memory cell array (10) includes multiple resistive memory cells (11-1-11-k). A write driver supplies a predetermined current to the resistive memory cells corresponding to multiple local bit lines through multiple global bit lines, respectively. Multiple first switches connect multiple word lines to a ground line in response to a first switch control signal. Multiple second switches connect the global bit lines to the local bit lines in response to a second switch control signal.
Abstract translation: 目的：电阻式存储器件及其操作方法以及包括其的存储器系统通过阻止流过存储单元的电流来改善存储单元的分布。 构成：存储单元阵列（10）包括多个电阻存储单元（11-1-11-k）。 写入驱动器分别通过多个全局位线向与多个本地位线对应的电阻存储单元提供预定电流。 多个第一开关响应于第一开关控制信号将多个字线连接到地线。 多个第二开关响应于第二开关控制信号将全局位线连接到本地位线。
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公开(公告)号：KR1020130021706A
公开(公告)日：2013-03-06
申请号：KR1020110084137
申请日：2011-08-23
Applicant: 삼성전자주식회사
CPC classification number: G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/0076 , G11C2013/0092 , G11C16/10
Abstract: PURPOSE: A write signal generating circuit, a variable resistance memory device including the same, and a driving method thereof are provided to improve data write performance by minimizing the setup time of a write current. CONSTITUTION: A pre-emphasis signal generating circuit(160) receives the location information of a program target memory cell and generates a pre-emphasis signal according to the location information of the program target memory cell. A write driver(130) generates a program signal corresponding to data programmed in the program target memory cell. The write driver generates a write signal by adding the program signal to the pre-emphasis signal from the pre-emphasis signal generating circuit and outputs the write signal to the program target memory cell.
Abstract translation: 目的：提供写入信号发生电路，包括该写入信号发生电路的可变电阻存储器件及其驱动方法，以通过最小化写入电流的建立时间来提高数据写入性能。 构成：预加重信号生成电路（160）接收节目对象存储单元的位置信息，根据节目对象存储单元的位置信息生成预加重信号。 写入驱动器（130）产生与编程在程序目标存储器单元中的数据相对应的程序信号。 写入驱动器通过将编程信号加到来自预加重信号产生电路的预加重信号来产生写信号，并将写信号输出到程序目标存储单元。
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公开(公告)号：KR1020120012709A
公开(公告)日：2012-02-10
申请号：KR1020100074894
申请日：2010-08-03
Applicant: 삼성전자주식회사
CPC classification number: G11C7/12 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/004 , G11C5/14 , G11C7/1048 , G11C16/26
Abstract: PURPOSE: A memory device, a precharge controlling method thereof, and apparatuses including the same are provided to reduce RC delay of a global bit line by arranging a precharge circuit between sub arrays. CONSTITUTION: A memory cell array includes a plurality of sub arrays(21-1,21-2). One or more first precharge circuits(22-1,22-2) are formed in the memory cell array. At least one first precharge circuit precharges the selected global bit line with the first precharge voltage. A second precharge circuit(24) is formed outside the memory cell array and precharges the selected global bit line with a second precharge voltage.
Abstract translation: 目的：提供一种存储器件，其预充电控制方法和包括该存储器件的装置，以通过在子阵列之间布置预充电电路来减小全局位线的RC延迟。 构成：存储单元阵列包括多个子阵列（21-1,21-2）。 一个或多个第一预充电电路（22-1,22-2）形成在存储单元阵列中。 至少一个第一预充电电路用第一预充电电压对所选择的全局位线进行预充电。 第二预充电电路（24）形成在存储单元阵列的外部，并且以第二预充电电压对所选择的全局位线进行预充电。
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