웨이퍼 정렬 장치
    2.
    发明公开
    웨이퍼 정렬 장치 无效
    SOG过程中的波形对准系统,其中心引脚在恒定间隔中安装

    公开(公告)号:KR1020040076733A

    公开(公告)日:2004-09-03

    申请号:KR1020030012074

    申请日:2003-02-26

    Inventor: 송재원

    Abstract: PURPOSE: A wafer alignment system is provided to correct stably a position of a wafer by installing centering pins in a constant interval around a plate. CONSTITUTION: A wafer is loaded on an upper surface of a plate(100). A plurality of centering pins(200) are installed in a constant interval around the plate in order to align the wafer to a center part of the plate. A driving part(300) drives the centering pins. The driving part is formed with one of a pneumatic cylinder, a hydraulic cylinder, and a stepping motor. The centering pins are moved by the driving unit. The centering pins are used for aligning a flat zone of the wafer on the center of the centering pins.

    Abstract translation: 目的:提供晶片对准系统,通过以围绕板的恒定间隔安装定心销来稳定地校正晶片的位置。 构成:将晶片装载在板(100)的上表面上。 多个定心销(200)以恒定间隔安装在板周围,以便将晶​​片对准该板的中心部分。 驱动部件(300)驱动定心销。 驱动部分由气缸,液压缸和步进电机中的一个形成。 定心销由驱动单元移动。 定心销用于对准定心销中心的晶片的平坦区域。

    반도체 소자의 층간절연막 평탄화방법
    3.
    发明公开
    반도체 소자의 층간절연막 평탄화방법 无效
    半导体器件的层间电介质的平面化方法

    公开(公告)号:KR1020040048491A

    公开(公告)日:2004-06-10

    申请号:KR1020020076244

    申请日:2002-12-03

    Abstract: PURPOSE: A planarization method of an inter layer dielectric of a semiconductor device is provided to be capable of simplifying a planarization process by using a spin coating method and reducing heat budgets as a reflow process is carried out. CONSTITUTION: A cell region is formed in a semiconductor substrate for forming a semiconductor memory. A storage poly and plate poly are formed in the cell region. A peripheral circuit is formed in a peripheral region in the semiconductor substrate. An inter layer dielectric(20) is deposited on the entire surface of the resultant structure. A spin coating oxide layer(22) is formed on the resultant structure. A dry etching process is carried out at the resultant structure for partially removing the inter layer dielectric in the cell region and the spin coating oxide layer in the peripheral region.

    Abstract translation: 目的:提供半导体器件的层间电介质的平面化方法,以便能够通过使用旋涂法简化平坦化处理,并且在进行回流处理时可以减少热量预算。 构成:在用于形成半导体存储器的半导体衬底中形成单元区域。 在电池区域中形成存储的聚和多晶硅。 外围电路形成在半导体衬底的周边区域中。 在所得结构的整个表面上沉积层间电介质(20)。 在所得结构上形成旋涂氧化物层(22)。 在所得结构中进行干蚀刻处理,以部分去除晶胞区域中的层间电介质和周边区域中的旋涂氧化物层。

    아날로그-디지털 컨버터 및 이를 포함하는 전자 시스템
    4.
    发明公开
    아날로그-디지털 컨버터 및 이를 포함하는 전자 시스템 有权
    模拟数字转换器和包括它的电子系统

    公开(公告)号:KR1020100085572A

    公开(公告)日:2010-07-29

    申请号:KR1020090004944

    申请日:2009-01-21

    CPC classification number: H03M1/141 H03M7/165

    Abstract: PURPOSE: By including the first logic generating the first digital code and the second logic generating the second digital code the analog digital converter and electronic system can eliminate the malfunction generating based on the switching operation of being required in the encoding process. CONSTITUTION: The first logic receives a message a plurality of thermometer codes and a plurality of reverse thermometer codes created based on the received analog signal. The first logic generates first digital codes of the multiple having the repeatability in which the cloth is similar based on location of received a plurality of thermometer codes and plurality of reverse thermometer code each logical values. The second logic receives a message a plurality of first digital codes.

    Abstract translation: 目的:通过包括产生第一数字码的第一逻辑和产生第二数字码的第二逻辑,模拟数字转换器和电子系统可以基于在编码过程中所需的切换操作来消除故障生成。 构成:第一逻辑接收消息,基于所接收的模拟信号创建多个温度计代码和多个反向温度计代码。 第一逻辑基于接收到多个温度计代码的位置和多个反向温度计代码生成每个逻辑值,从而产生具有布重复性的第一数字代码。 第二逻辑接收消息多个第一数字码。

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