公开(公告)号：KR101049254B1

公开(公告)日：2011-07-13

申请号：KR1020070014934

申请日：2007-02-13

Applicant: 삼성전자주식회사

Inventor： 신재필 ,  최진숙 ,  하정환 ,  유문현 ,  이종배

IPC: C12Q1/68 ,  C12Q1/00

CPC classification number: G03F1/36 ,  G03F1/00

Abstract: 마이크로 어레이의 프로브를 인-시츄 합성하기 위한 마스크 세트, 마스크 세트의 제조 방법, 및 마스크 세트를 이용한 마이크로 어레이의 제조 방법이 제공된다. 마이크로 어레이용 마스크 세트는 복수의 어레이된 프로브 셀을 포함하는 기판 상에 프로브를 인-시츄 합성하기 위한 복수의 마스크로서, 각 마스크는 투광 영역 및 차광 영역을 포함하고, 프로브 셀은 투광 영역 및 차광 영역 중 어느 하나와 대응하고, 투광 영역의 패턴은 인접하는 다른 투광 영역에 따라 광 근접 효과가 보정되어 있는 패턴인 복수의 마스크를 포함한다.
마스크 세트, 마스크 레이아웃, 투광 영역, 세리프

公开(公告)号：KR100817065B1

公开(公告)日：2008-03-27

申请号：KR1020060097409

申请日：2006-10-02

Applicant: 삼성전자주식회사

Inventor： 신재필 ,  김영일 ,  유문현 ,  이종배

IPC: H01L21/027

CPC classification number: G03F1/36 ,  G03F1/144 ,  G03F1/30 ,  G03F1/38

Abstract: A method for designing a fine pattern is provided to transfer a fine pattern as it is to a material by forming a sub pattern for substantially transferring a fine pattern for exposure. The original data of a fine pattern for exposure is read out. The fine pattern is divided into first and second patterns wherein the first pattern needn't to be corrected and the second pattern needs to be corrected. A sub pattern is formed to maintain a first distance with the second pattern so that the fine pattern is corrected. A program including the first pattern, the second pattern and the sub pattern is performed to predict a fine pattern to be transferred to a material. The predicted fine pattern is compared with the original data, and the corrected fine pattern is determined to be a final fine pattern if any difference exists between the predicted fine pattern and the original data. The sub pattern can be a first sub pattern that is independently disposed and maintains the first distance with the second pattern having a width of W1.

Abstract translation: 提供一种设计精细图案的方法，通过形成用于基本转印用于曝光的精细图案的子图案，将精细图案原样转印到材料上。 读出用于曝光的精细图案的原始数据。 精细图案被分为第一图案和第二图案，其中第一图案不需要被校正，并且第二图案需要被校正。 形成子图案以保持与第二图案的第一距离，使得精细图案被校正。 执行包括第一图案，第二图案和子图案的程序以预测要传送到材料的精细图案。 将预测的精细图案与原始数据进行比较，并且如果在预测的精细图案和原始数据之间存在任何差异，则校正的精细图案被确定为最终精细图案。 子图案可以是独立设置的第一子图案，并且与第二图案保持第一距离，宽度为W1。

公开(公告)号：KR100378195B1

公开(公告)日：2003-03-29

申请号：KR1020010008757

申请日：2001-02-21

Applicant: 삼성전자주식회사

Inventor： 신재필 ,  유광재 ,  박상호 ,  유문현

IPC: H01L21/027

CPC classification number: H01L21/76819 ,  G03F1/36 ,  G06F17/5068 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Dummy patterns are generated for a region of an integrated circuit that is divided into buckets by obtaining a local pattern density for a respective bucket and adjusting a density of the dummy pattern for the respective bucket as a continuously variable function of the respective local pattern density and a target density for the region. By providing a continuously variable dummy pattern density, the desired density of the dummy pattern group may be adjusted precisely, to thereby reduce or eliminate loading effects. The density of the dummy pattern for the respective bucket may be calculated according to a formula in which the density of the dummy pattern is continuously variable. The dummy patterns may include features of fixed pitch and a size of the features of fixed pitch is increased or decreased as a continuously variable function of the respective local pattern density and the target density for the region.

Abstract translation: 通过获得各个桶的局部图案密度并且将各个桶的虚拟图案的密度调节为各个局部图案密度的连续可变函数，并且将各个局部图案密度的连续可变函数和 该地区的目标密度。 通过提供连续变化的虚设图案密度，可以精确地调整虚设图案组的期望密度，从而减少或消除加载效应。 可以根据虚拟图案的密度连续可变的公式来计算用于各个桶的虚拟图案的密度。 虚设图案可以包括固定节距的特征，并且固定间距的特征的尺寸被增大或减小为各个局部图案密度和该区域的目标密度的连续可变函数。

公开(公告)号：KR101757743B1

公开(公告)日：2017-07-17

申请号：KR1020110019097

申请日：2011-03-03

Applicant: 삼성전자주식회사

Inventor： 이영미 ,  김인성 ,  박지숭 ,  안병섭 ,  신재필

IPC: H01L21/027

CPC classification number: G03F1/36 ,  G03F1/22 ,  G03F1/68 ,  G03F1/70 ,  G03F1/84 ,  G03F7/70433 ,  G03F7/70441 ,  G03F7/70591 ,  G03F7/70941

Abstract: 본발명의사상에의한플레어보정방법및 EUV 마스크제조방법은 EUV 리소그라피공정에서의플레어효과에의한 CD(Critical Dimension) 에러를방지할수 있는방법및 그러한플레어효과를보정할수 있는 EUV 마스크제조방법을제공한다. 그플레어보정방법은테스트패턴에대한플레어(flare)를측정하는단계; 상기플레어에대한 PSF(Point Spread Function)을계산하는단계; 및작용범위(influence range)에따른각각의상기 PSF를이용하여상기플레어를각각보정하는단계;를포함한다.

公开(公告)号：KR100819006B1

公开(公告)日：2008-04-03

申请号：KR1020070014896

申请日：2007-02-13

Applicant: 삼성전자주식회사

Inventor： 신재필 ,  최진숙 ,  유문현 ,  이종배

IPC: C12Q1/68 ,  C12Q1/00

CPC classification number: C40B40/06 ,  B01J19/0046 ,  B01J2219/00432 ,  B01J2219/00497 ,  B01J2219/00527 ,  B01J2219/00585 ,  B01J2219/00596 ,  B01J2219/00605 ,  B01J2219/00659 ,  B01J2219/00675 ,  B01J2219/00689 ,  B01J2219/00693 ,  B01J2219/00695 ,  B01J2219/00711 ,  B01J2219/00722 ,  B01J2219/00725 ,  B82Y30/00 ,  C40B40/10 ,  C40B50/14 ,  C40B60/14 ,  C12Q1/6837 ,  C12Q1/6841

Abstract: A mask set is provided to have a controlled area of a transparent region. A system and a method for determining a mask layout are provided to control the area of the transparent region of the mask layout to have the same or larger area than minimum transparent region without changing sequences of a probe to be synthesized, thereby improving the pattern reliability of the mask set. A mask set comprises a plurality of masks for in situ synthesizing a probe of a microarray, wherein each of the mask includes a transparent region and a shielding region and the area of the transparent region regarding the total area of the transparent region and the shielding region is more than 5%. A system for determining a mask layout comprises: a pattern determining portion which provides the transparent region and the shielding region to a plurality of mask layouts for in situ synthesizing the probe of the microarray; a selection portion which selects one of the mask layouts; a comparison portion which compares the transparent region area of the selected mask layout with a minimum transparent area; and a pattern changing portion which exchanges the selected shielding region of the selected mask layout with the pattern changing portion of the transparent region of the non-selected mask layout when the transparent region of the selected mask layout is smaller than the minimum transparent region. A method for preparing the microarray comprises the steps of: (a) providing a substrate including a plurality of arrayed probe cells and the surface being protected by a photodegradable protecting group; and (b) in situ synthesizing the probe of the microarray using the mask set, wherein each the transparent region and the shielding region corresponds to the probe cell of the microarray. Further, an area of the probe cells is 100mum or more.

Abstract translation: 提供掩模组以具有透明区域的受控区域。 提供一种用于确定掩模布局的系统和方法，用于控制掩模布局的透明区域的面积与最小透明区域相同或更大的面积，而不改变要合成的探针的序列，从而提高图案可靠性 的面具套。 掩模组包括用于原位合成微阵列探针的多个掩模，其中每个掩模包括透明区域和屏蔽区域，并且透明区域的面积相对于透明区域和屏蔽区域的总面积 超过5％。 一种用于确定掩模布局的系统包括：图形确定部分，其将透明区域和屏蔽区域提供给多个掩模布局，用于原位合成微阵列的探针; 选择部分，其选择所述掩模布局之一; 将所选择的掩模布局的透明区域区域与最小透明区域进行比较的比较部分; 以及图案改变部，当所选择的掩模布局的透明区域小于最小透明区域时，将所选择的掩模布局的所选择的屏蔽区域与未选择的掩模布局的透明区域的图案改变部分交换。 一种制备微阵列的方法包括以下步骤：（a）提供包括多个排列的探针细胞的基底，该表面被可光降解的保护基保护; 和（b）使用掩模组原位合成微阵列的探针，其中每个透明区域和屏蔽区域对应于微阵列的探针单元。 此外，探针单元的面积为100μm以上。

公开(公告)号：KR100817064B1

公开(公告)日：2008-03-27

申请号：KR1020060097408

申请日：2006-10-02

Applicant: 삼성전자주식회사

Inventor： 신재필 ,  김영일 ,  유문현

IPC: H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/0335

Abstract: A mask for forming a fine pattern is provided to normally transfer first and second patterns on a mask to a transfer target material during a dual patterning process by forming a sub pattern capable of maintaining a first distance between the first and second patterns. First patterns are repeated in a first direction. Second patterns(202) with a first width are arranged in parallel with the first pattern, positioned between the first patterns. A sub pattern is disposed between the first and second patterns, maintaining a first distance with the second pattern. The sub pattern can be a first sub pattern(208) that is independently disposed and maintains the first distance with the second pattern.

Abstract translation: 提供了用于形成精细图案的掩模，以通过形成能够保持第一和第二图案之间的第一距离的子图案，在双重图案化工艺期间将掩模上的第一图案和第二图案正常地转印到转印对象材料上。 第一图案在第一方向上重复。 具有第一宽度的第二图案（202）与第一图案平行布置，位于第一图案之间。 子图案设置在第一和第二图案之间，与第二图案保持第一距离。 子图案可以是独立地设置并与第二图案保持第一距离的第一子图案（208）。

公开(公告)号：KR101487370B1

公开(公告)日：2015-01-30

申请号：KR1020080065397

申请日：2008-07-07

Applicant: 삼성전자주식회사

Inventor： 김영일 ,  유문현 ,  이종배 ,  신재필

IPC: H01L21/027 ,  H01L21/28

CPC classification number: G06F17/5068

Abstract: 마스크 레이아웃 형성 방법에 있어서, 제1 선폭 이상을 갖는 배선을 형성하기 위한 배선 영역을 설정한 후, 상기 배선 영역을, 제1 영역 및 상기 배선과 전기적으로 연결되는 콘택을 형성하기 위한 콘택 영역들을 갖는 제2 영역으로 구획한다. 상기 제1 영역 내에 제1 더미 패턴들을 형성하기 위한 제1 더미 영역들을 설정한다. 이어서, 상기 제2 영역 중 상기 콘택 영역들 사이에, 제2 더미 패턴들을 형성하기 위한 제2 더미 영역들을 설정한다. 따라서, 금속 배선을 형성하기 위한 다마신 공정 중 평탄화에서의 디싱 현상이 억제되도록 절연막 구조물을 형성하기 위한 마스크의 레이아웃이 형성된다.

公开(公告)号：KR1020130129639A

公开(公告)日：2013-11-29

申请号：KR1020120053669

申请日：2012-05-21

Applicant: 삼성전자주식회사

Inventor： 강창우 ,  신재필 ,  서상원 ,  정대현

IPC: G06F9/46 ,  G06F9/38

CPC classification number: G06F17/30079 ,  G06F17/5068

Abstract: A file merging system of which the processing speed is fast is provided. The file merging system comprises a first and a second input disk, an output disk, and a processing connected to the input and output disks. The first input disk and a second input disk include a first layout input file including a plurality of first type cell records and a second layout input file including a plurality of second type cell records respectively. The processor lights the first and second cell records without modification.

Abstract translation: 提供处理速度快的文件合并系统。 文件合并系统包括第一和第二输入盘，输出盘和连接到输入和输出盘的处理。 第一输入盘和第二输入盘包括分别包括多个第一类型单元记录的第一布局输入文件和包括多个第二类型单元记录的第二布局输入文件。 处理器照亮第一和第二个单元格记录，而无需修改。

公开(公告)号：KR1020080075683A

公开(公告)日：2008-08-19

申请号：KR1020070014934

申请日：2007-02-13

Applicant: 삼성전자주식회사

Inventor： 신재필 ,  최진숙 ,  하정환 ,  유문현 ,  이종배

IPC: C12Q1/68 ,  C12Q1/00

CPC classification number: G03F1/36 ,  G03F1/00 ,  G03F1/144 ,  B01J19/0046 ,  C12Q1/6837 ,  C12Q1/6841

Abstract: A mask set for in-situ synthesis of probes of a microarray is provided to permit accurate exposure to the edge of probe cells by adding the optical proximity correction pattern, wherein a transparent portion of each mask reflects the effects of adjacent transparent portion, so that reliability of the probe in-situ synthesis is improved. A plurality of masks for in situ synthesis of probes on a substrate containing a plurality of arrayed probe cells contain a transparent portion and a non-transparent portion in each mask, wherein the probe cell corresponds to any one of the transparent portion and non-transparent portion of each mask; and the transparent portion pattern is a pattern having corrected optical proximity effects. A method for fabricating the mask set for microarray comprises the steps of: providing a plurality of mask layouts containing a transparent portion and a non-transparent portion, wherein the probe cell corresponds to any one of the transparent portion and non-transparent portion of each mask; performing optical proximity effects correction for the transparent portion pattern of each mask layout; and fabricating a plurality of masks by using each mask layout performing the optical proximity effects correction.

Abstract translation: 提供用于原位合成微阵列探针的掩模组，以允许通过添加光学邻近校正图案来准确地暴露于探针单元的边缘，其中每个掩模的透明部分反映相邻透明部分的影响，使得 探针原位合成的可靠性得到改善。 用于在包含多个排列的探针单元的基板上原位合成探针的多个掩模包含每个掩模中的透明部分和不透明部分，其中探针单元对应于透明部分和不透明的任何一个 每个面罩的一部分; 并且透明部分图案是具有校正的光学邻近效应的图案。 制造微阵列掩模组的方法包括以下步骤：提供包含透明部分和不透明部分的多个掩模布局，其中探针单元对应于每个透明部分和不透明部分中的任一个 面具; 对每个掩模布局的透明部分图案执行光学邻近效应校正; 以及通过使用执行光学邻近效应校正的每个掩模布局来制造多个掩模。

公开(公告)号：KR1020160006420A

公开(公告)日：2016-01-19

申请号：KR1020140085953

申请日：2014-07-09

Applicant: 삼성전자주식회사

Inventor： 신재필 ,  강창우 ,  김종원 ,  이호준 ,  장규백 ,  정원영

IPC: H01L21/66 ,  H01L21/00

CPC classification number: G06F17/5081 ,  G06F17/5009

Abstract: 서로다른물질들로형성되는제1 및제2 패턴들을포함하는집적회로의스트레스를검출하는방법에서, 상기제1 패턴의적어도하나의스트레스검출포인트가결정되고, 상기스트레스검출포인트를포함하는영역이복수의분할영역들로분할되며, 상기복수의분할영역들에서의상기제2 패턴의면적들이각각계산되며, 상기복수의분할영역들에서의상기제2 패턴의면적들에기초하여상기스트레스검출포인트에서상기제2 패턴에의한상기제1 패턴에대한스트레스레벨이검출된다. 이에따라, 집적회로의스트레스검출이신속하게수행될수 있고, 집적회로의전체영역에서의스트레스를검출하는풀-칩스트레스시뮬레이션이수행될수 있다.

Abstract translation: 一种用于检测包括由彼此不同的材料形成的第一和第二图案的集成电路的应力的方法包括：确定所述第一图案的至少一个应力检测点; 将包括应力检测点的区域划分为多个分割区域; 计算划分区域中第二种模式的各个区域; 并且基于分割区域中的第二图案的区域，在应力检测点处检测第一图案的第二图案的应力水平。 因此，可以快速地检测集成电路的应力，并且可以进行用于检测集成电路的整个区域中的应力的全芯片应力模拟。