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公开(公告)号：KR1020140100752A
公开(公告)日：2014-08-18
申请号：KR1020130013878
申请日：2013-02-07
Applicant: 삼성전자주식회사
CPC classification number: G11C8/06 , G11C5/04 , G11C7/1045
Abstract: According to the present invention, a memory module includes a plurality of semiconductor memory devices. Each of the semiconductor memory devices includes a memory cell array which includes a plurality of memory cells arranged in a region where a plurality of bit lines and a plurality of word lines cross each other; a mode register set (MRS) circuit which generates an enable signal corresponding to an error generation mode for each of the semiconductor memory devices in response to an MRS command applied from a command decoder; and an address buffer which compares an address signal inputted from the outside with a prestored, predetermined address signal, based on the enable signal. When the address signal inputted from the outside is identical with the predetermined address signal, data other than data inputted from the outside is written to a memory cell corresponding to the predetermined address signal.
Abstract translation: 根据本发明，存储器模块包括多个半导体存储器件。 每个半导体存储器件包括存储单元阵列，该存储单元阵列包括布置在多个位线和多个字线交叉的区域中的多个存储单元; 模式寄存器组（MRS）电路，响应于从命令解码器施加的MRS命令，产生对应于每个半导体存储器件的误差产生模式的使能信号; 以及地址缓冲器，其根据使能信号将从外部输入的地址信号与预先存储的预定地址信号进行比较。 当从外部输入的地址信号与预定地址信号相同时，从外部输入的数据以外的数据被写入与预定地址信号对应的存储单元。
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公开(公告)号：KR1020150135004A
公开(公告)日：2015-12-02
申请号：KR1020140062607
申请日：2014-05-23
Applicant: 삼성전자주식회사
CPC classification number: G11C8/10 , G11C5/04 , G11C11/401 , G11C29/08 , G11C29/26
Abstract: 본발명은어드레스미러링기능을갖는메모리모듈에대하여개시된다. 메모리모듈은, 랭크머지드테스트모드시, 한번의 MRS 커맨드에응답하여제1 랭크의제1 메모리칩들과제2 랭크의제2 메모리칩들의모드레지스터들이동일하게프로그램되도록하는레지스터를포함한다. 레지스터는인쇄회로기판의 TVH 또는 BVH를통하여서로대칭적으로연결되는어드레스신호들이선택적으로미러링되도록설정한다.
Abstract translation: 根据本发明，公开了一种具有地址镜像功能的存储器模块。 存储器模块包括：寄存器，其使能第一等级的第一存储器芯片的模式寄存器和第二等级的第二存储器芯片的模式寄存器在等级合并期间响应于模式寄存器集（MRS）命令被相同地编程 测试模式。 寄存器设置通过印刷电路板的TVH或BVH对称连接的地址信号以进行选择性镜像。
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公开(公告)号：KR1020140021419A
公开(公告)日：2014-02-20
申请号：KR1020120087948
申请日：2012-08-10
Applicant: 삼성전자주식회사
CPC classification number: G01R31/02 , G01R31/01 , G01R31/26 , G01R31/27 , G06F13/28 , G06F17/5054 , G11C5/04 , G11C7/1012 , G11C7/1021 , G11C7/1036 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/406 , G11C11/4096 , G11C29/02 , G11C29/1201 , G11C29/14 , G11C2029/0401 , G11C2029/4002 , H03M7/40 , H03M13/00
Abstract: A memory module according to the present invention comprises a plurality of semiconductor memory devices. Each of the semiconductor memory devices includes: a memory cell array including a plurality of memory cells disposed in an area in which a plurality of bit lines and a plurality of word lines cross each other; and a data input/output circuit configured to receive data input from the outside, output the received data to the memory cell array, receive data read from the memory cell array, and output the read data to the outside, wherein the data input from the outside includes data information corresponding to the data, and the data input/output circuit outputs data corresponding to predetermined bit values in the order of a plurality of input/output lines, based on the bit values included in the data information. [Reference numerals] (110) Memory cell array; (120) Row decoder; (130) Sense amplifier; (140) Column decoder; (150) Refresh control circuit; (160) Command decoder; (180) Address buffer; (190) Data input/output circuit
Abstract translation: 根据本发明的存储器模块包括多个半导体存储器件。 每个半导体存储器件包括：存储单元阵列，包括设置在多个位线和多个字线交叉的区域中的多个存储单元; 以及数据输入/输出电路，被配置为接收从外部输入的数据，将接收到的数据输出到存储单元阵列，接收从存储单元阵列读取的数据，并将读取的数据输出到外部，其中从 外部包括对应于数据的数据信息，并且数据输入/输出电路基于包括在数据信息中的比特值，输出与多个输入/输出线的顺序对应的预定比特值的数据。 （附图标记）（110）存储单元阵列; （120）行解码器; （130）感应放大器; （140）列解码器; （150）刷新控制电路; （160）命令解码器; （180）地址缓冲区; （190）数据输入/输出电路
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