公开(公告)号：KR100375231B1

公开(公告)日：2003-03-08

申请号：KR1020010008131

申请日：2001-02-19

Applicant: 삼성전자주식회사

Inventor： 신광식 ,  양희홍

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/66825

Abstract: A method of fabricating a non-volatile memory device having a U-shaped floating gate is described. This method forms a device isolation layer in a predetermined region of a semiconductor substrate, thereby defining at least one active region. A floating gate pattern covering active regions and having a gap region exposing the device isolation layer therebetween is formed, and an insulation material pattern where the width of a projection is wider than an upper width of the gap region while the projection covers the gap region and is higher then an upper surface of the floating gate pattern is formed. Subsequently, the floating gate pattern is etched using the insulation material pattern, thereby forming a modified floating gate pattern showing a U-shaped cross section on an active region. As a result, a coupling ratio of the non-volatile memory device can be increased.

Abstract translation: 描述了制造具有U形浮动栅极的非易失性存储器件的方法。 该方法在半导体衬底的预定区域中形成器件隔离层，从而限定至少一个有源区。 形成覆盖有源区域并具有暴露出其间的器件隔离层的间隙区域的浮置栅极图案，以及绝缘材料图案，其中突出部的宽度大于间隙区域的上部宽度，同时突出部覆盖间隙区域，以及 高于浮栅图案的上表面。 随后，使用绝缘材料图案来蚀刻浮置栅极图案，从而在有源区上形成显示出U形横截面的修改的浮置栅极图案。 结果，可以增加非易失性存储器件的耦合比率。

公开(公告)号：KR1020020059473A

公开(公告)日：2002-07-13

申请号：KR1020010000851

申请日：2001-01-06

Applicant: 삼성전자주식회사

Inventor： 신광식 ,  양희홍

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

Abstract: PURPOSE: A method for manufacturing a flash memory cell having a floating gate is provided to gain a high coupling ratio while increasing the integration degree. CONSTITUTION: A trench area is formed and an active area is defined by successively patterning a polishing stopping film, a first conductive layer(14a), a tunnel oxide film(17) and a semiconductor substrate(24). A device isolation film(15) is formed in the trench area and the polishing barrier film of an upper part of the active area is removed. A sacrificial insulation film pattern(23) composed of an oxide film pattern(21) and an etching barrier film(20) is formed on the device isolation film. The second conductive film(14b) is formed on the results formed by the sacrificial insulation film. An insulation material film is formed within a gab area of the second conductive film surrounding the sacrificial insulation pattern. The upper surface of the sacrificial insulation film is exposed and a floating gate pattern(14) having a cross section of a 'U' shape is formed on the active area by selectively etching the sacrificial insulation film pattern.

Abstract translation: 目的：提供一种制造具有浮动栅极的闪存单元的方法，以在增加积分度的同时获得高耦合比。 构成：形成沟槽区域，并且通过连续构图抛光停止膜，第一导电层（14a），隧道氧化膜（17）和半导体衬底（24）来限定有源区。 在沟槽区域中形成器件隔离膜（15），去除有源区域的上部的抛光阻挡膜。 在器件隔离膜上形成由氧化膜图案（21）和蚀刻阻挡膜（20）构成的牺牲绝缘膜图案（23）。 在由牺牲绝缘膜形成的结果上形成第二导电膜（14b）。 绝缘材料膜形成在围绕牺牲绝缘图案的第二导电膜的加槽区域内。 牺牲绝缘膜的上表面被暴露，并且通过选择性地蚀刻牺牲绝缘膜图案，在有源区上形成具有“U”形横截面的浮栅图案（14）。

公开(公告)号：KR100366633B1

公开(公告)日：2003-01-09

申请号：KR1020000061987

申请日：2000-10-20

Applicant: 삼성전자주식회사

Inventor： 이석주 ,  양희홍 ,  남정림

IPC: H01L21/28

CPC classification number: H01L21/76807 ,  H01L21/76813

Abstract: A method of forming a contact hole for a dual damascene interconnection of a semiconductor device includes forming a first photoresist layer pattern on an insulating layer of a semiconductor substrate, the first photoresist layer pattern having a first opening with a first width. A groove having the first width to a prescribed depth of the insulating layer is formed by performing an etching process using the first photoresist layer pattern as an etch mask. A second photoresist layer pattern on the insulating layer having the groove therein is formed. The second photoresist layer has a second opening with a second width, wherein the second width is substantially equal to or larger than the first width of the groove. A contact hole exposing the semiconductor substrate is formed by performing an etching process using the second photoresist layer pattern as an etch mask.

Abstract translation: 一种形成用于半导体器件的双镶嵌互连的接触孔的方法包括在半导体衬底的绝缘层上形成第一光致抗蚀剂层图案，第一光致抗蚀剂层图案具有第一宽度的第一开口。 通过使用第一光致抗蚀剂层图案作为蚀刻掩模执行蚀刻工艺来形成具有第一宽度到绝缘层的规定深度的凹槽。 在其中形成有凹槽的绝缘层上形成第二光致抗蚀剂层图案。 第二光致抗蚀剂层具有第二宽度的第二开口，其中第二宽度基本上等于或大于凹槽的第一宽度。 通过使用第二光刻胶层图案作为蚀刻掩模执行蚀刻工艺来形成暴露半导体衬底的接触孔。

公开(公告)号：KR1020020067787A

公开(公告)日：2002-08-24

申请号：KR1020010008131

申请日：2001-02-19

Applicant: 삼성전자주식회사

Inventor： 신광식 ,  양희홍

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/66825

Abstract: PURPOSE: A method for fabricating a non-volatile memory(NVM) device is provided to maximize an area in which a floating gate and a control gate electrode are overlapped by forming a U-typed floating gate without increasing a cell area so that a low operating voltage and a fast operating characteristic are realized. CONSTITUTION: An isolation layer is formed in a predetermined region of a semiconductor substrate(100) to define at least one active region. A floating gate pattern having a gap region which covers the active regions and exposes the isolation layer between the active regions, is formed. The gap region is filled with an insulating material pattern having a protrusion higher than the upper surface of the floating gate pattern, in which the protrusion is wider than the upper portion of the gap region. The floating gate pattern is etched to form a floating gate pattern having a U-typed section in the active region by using the insulating material pattern as an etch mask. The insulating material pattern is eliminated. A gate interlayer dielectric(109) and a control gate electrode layer(110) are sequentially formed on the resultant structure from which the insulating material pattern is removed.

Abstract translation: 目的：提供一种用于制造非易失性存储器（NVM）器件的方法，以通过形成U型浮动栅极来最大化浮动栅极和控制栅电极重叠的区域，而不增加单元面积，使得低 实现了工作电压和快速工作特性。 构成：在半导体衬底（100）的预定区域中形成隔离层以限定至少一个有源区。 形成具有覆盖有源区域并且在有源区域之间暴露隔离层的间隙区域的浮栅图案。 间隙区域填充有突起比浮动栅极图案的上表面高的突起比间隙区域的上部更宽的绝缘材料图案。 通过使用绝缘材料图案作为蚀刻掩模，蚀刻浮栅图案以形成在有源区中具有U型截面的浮栅图案。 消除绝缘材料图案。 在除去绝缘材料图案的所得结构上依次形成栅极层间电介质（109）和控制栅电极层（110）。

公开(公告)号：KR1020020064452A

公开(公告)日：2002-08-09

申请号：KR1020010004908

申请日：2001-02-01

Applicant: 삼성전자주식회사

Inventor： 양희홍

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

Abstract: PURPOSE: A floating electrode formation method of flash memories is provided to reduce a bridge between floating electrodes and to solve a field down problem in O/N/O(Oxide/Nitride/Oxide) etch processing by improve a structure. CONSTITUTION: The first poly spacers(21) are formed on both sides of oxides(3) filled in trenches after removing a CMP(Chemical Mechanical Polishing) stopping SiN on the first polysilicon. At this time, a C/R(Coupling Ratio) of a floating electrode is more secured. After partially removing the oxides(3), the second poly spacers(23) are formed at both sides of the first poly spacers(21) in each trench region. Then, a photoresist pattern(25) is completely removed and floating electrode structures are formed. At this time, the floating electrode structures solve a misalign problem between self-aligned trenches and floating electrodes.

Abstract translation: 目的：提供闪存的浮动电极形成方法以减少浮置电极之间的桥接，并通过改进结构来解决O / N / O（氧化物/氮化物/氧化物）蚀刻处理中的场下降问题。 构成：在去除第一多晶硅上的CMP（化学机械抛光）停止SiN之后，第一聚合间隔物（21）形成在填充在沟槽中的氧化物（3）的两侧。 此时，浮动电极的C / R（耦合比）更加确保。 在部分去除氧化物（3）之后，在每个沟槽区域中的第一聚合间隔物（21）的两侧形成第二聚合物间隔物（23）。 然后，完全去除光致抗蚀剂图案（25），并形成浮动电极结构。 此时，浮置电极结构解决了自对准沟槽和浮置电极之间的对准问题。

公开(公告)号：KR1020020017181A

公开(公告)日：2002-03-07

申请号：KR1020000050357

申请日：2000-08-29

Applicant: 삼성전자주식회사

Inventor： 양희홍

IPC: H01L21/3205

Abstract: PURPOSE: A method for forming a contact hole for a dual damascene interconnection of a semiconductor device is provided to form a contact hole exposing a lower layer even if a photoresist layer is thick, by performing an etch process after sufficient selectivity is guaranteed. CONSTITUTION: The first and second intermetallic dielectrics are sequentially formed on a lower metal layer pattern(420) formed on a semiconductor substrate(400). The first photoresist layer pattern is formed on the second intermetallic dielectric. A part of the second intermetallic dielectric is removed by using the first photoresist layer pattern as an etch mask to form the second intermetallic dielectric pattern(445) exposing a partial surface of the first intermetallic dielectric. The first photoresist layer pattern is removed. A photoresist layer(460) covering the exposed surface of the first intermetallic dielectric and the second intermetallic dielectric pattern is formed. An exposure process is performed regarding the resultant structure. A selective substitution reaction is generated regarding the surface of the photoresist layer to form a passivation layer(465) on the photoresist layer in a non-exposed portion. A plasma etch process is performed by using the passivation layer as an etch mask to form the second photoresist layer pattern exposing a partial surface of the first intermetallic dielectric. The exposed portion of the first intermetallic dielectric is removed by using the second photoresist layer pattern as an etch mask to form the first intermetallic dielectric pattern exposing a part of the lower metal layer pattern. The second photoresist layer pattern is eliminated.

Abstract translation: 目的：提供一种用于形成半导体器件的双镶嵌互连的接触孔的方法，以便即使光致抗蚀剂层较厚，也可以通过在保证足够的选择性之后执行蚀刻工艺来形成露出下层的接触孔。 构成：第一和第二金属间电介质依次形成在形成在半导体衬底（400）上的下金属层图案（420）上。 第一光致抗蚀剂图案形成在第二金属间电介质上。 通过使用第一光致抗蚀剂层图案作为蚀刻掩模来去除部分第二金属间电介质，以形成暴露第一金属间电介质的部分表面的第二金属间介电图案（445）。 去除第一光致抗蚀剂层图案。 形成覆盖第一金属间电介质和第二金属间介电图案的暴露表面的光致抗蚀剂层（460）。 对所得到的结构进行曝光处理。 产生关于光致抗蚀剂层的表面的选择性取代反应，以在非曝光部分的光致抗蚀剂层上形成钝化层（465）。 通过使用钝化层作为蚀刻掩模来进行等离子体蚀刻工艺，以形成暴露第一金属间电介质的部分表面的第二光致抗蚀剂层图案。 通过使用第二光致抗蚀剂层图案作为蚀刻掩模来去除第一金属间介电层的暴露部分，以形成露出下部金属层图案的一部分的第一金属间介电图案。 消除第二光致抗蚀剂图案。

公开(公告)号：KR1020010047961A

公开(公告)日：2001-06-15

申请号：KR1019990052400

申请日：1999-11-24

Applicant: 삼성전자주식회사

Inventor： 양희홍 ,  김학

IPC: H01L21/027

Abstract: PURPOSE: A method for forming a line first dual damascene pattern with using an oxide mask layer is provided to allow a stable formation of a contact pattern. CONSTITUTION: In the method, an interlayer dielectric layer(31) having a lower metal layer(32) formed therein is formed on a semiconductor substrate. Next, the first and second insulating layers(33,34) are formed on the interlayer dielectric layer(31), and the first resist pattern is then formed thereon. Next, the second insulating layer(34) is selectively etched through the first resist pattern, and then the first resist pattern is removed. Thereafter, the second resist layer(36) is formed for planarization over an entire structure, and then the third insulating layer(37) is formed thereon and patterned. Next, the second resist layer(36) is also patterned through the patterned third insulating layer(37). Then, the first insulating layer(33) is selectively etched by using both the patterned third insulating layer(37) and the patterned second resist layer(36) as a mask, so that contact holes exposing portions of the lower metal layer(32) are formed therein. The third insulating layer(37) is preferably made of oxide.

Abstract translation: 目的：提供一种使用氧化物掩模层形成线第一双镶嵌图案的方法，以便能够稳定地形成接触图案。 构成：在该方法中，在半导体衬底上形成有形成有下金属层（32）的层间绝缘膜（31）。 接着，在层间电介质层（31）上形成第一和第二绝缘层（33,34），然后在其上形成第一抗蚀剂图案。 接下来，通过第一抗蚀剂图案选择性地蚀刻第二绝缘层（34），然后去除第一抗蚀剂图案。 此后，形成第二抗蚀剂层（36）以在整个结构上进行平面化，然后在其上形成图案化的第三绝缘层（37）。 接下来，第二抗蚀剂层（36）也通过图案化的第三绝缘层（37）图案化。 然后，通过使用图案化的第三绝缘层（37）和图案化的第二抗蚀剂层（36）作为掩模来选择性地蚀刻第一绝缘层（33），使得暴露下部金属层（32）的部分的接触孔 形成在其中。 第三绝缘层（37）优选由氧化物制成。

公开(公告)号：KR1020020031492A

公开(公告)日：2002-05-02

申请号：KR1020000061987

申请日：2000-10-20

Applicant: 삼성전자주식회사

Inventor： 이석주 ,  양희홍 ,  남정림

IPC: H01L21/28

CPC classification number: H01L21/76807 ,  H01L21/76813

Abstract: PURPOSE: A method of forming a contact hole for a dual damascene line of a semiconductor device is provided to prevent an opening error of a contact hole due to reduced optical intensity. CONSTITUTION: An oxide layer is formed on a semiconductor substrate(500). A photoresist layer pattern is formed on the oxide layer. An oxide layer pattern having a groove(530) is formed by using the photoresist layer pattern as an etch mask. The photoresist layer pattern is removed. A photoresist layer pattern is formed on the oxide layer pattern. The photoresist layer pattern has an opening portion for exposing a bottom of the groove(530) of the oxide layer pattern. An oxide layer pattern(512) having a contact hole(550) is formed by using the photoresist layer pattern as an etch mask. The photoresist layer pattern is removed. A metal layer is filled into the contact hole(550) and the groove(530).

Abstract translation: 目的：提供一种形成半导体器件的双镶嵌线的接触孔的方法，以防止由于光强度降低导致的接触孔的开启误差。 构成：在半导体衬底（500）上形成氧化物层。 在氧化物层上形成光致抗蚀剂图案。 通过使用光致抗蚀剂层图案作为蚀刻掩模来形成具有凹槽（530）的氧化物层图案。 去除光致抗蚀剂层图案。 在氧化物层图案上形成光致抗蚀剂图案。 光致抗蚀剂层图案具有用于暴露氧化物层图案的凹槽（530）的底部的开口部分。 通过使用光致抗蚀剂层图案作为蚀刻掩模，形成具有接触孔（550）的氧化物层图案（512）。 去除光致抗蚀剂层图案。 金属层填充到接触孔（550）和凹槽（530）中。

公开(公告)号：KR1020010017560A

公开(公告)日：2001-03-05

申请号：KR1019990033142

申请日：1999-08-12

Applicant: 삼성전자주식회사

Inventor： 양희홍

IPC: H01L21/28

Abstract: PURPOSE: A method for manufacturing a dual damascene structure is provided to prevent an edge of a contact hole from being damaged, by filling the contact hole with a photoresist layer, by forming an opening for forming an upper interconnection, and by eliminating the photoresist layer. CONSTITUTION: The second and third insulating layers(214,216) are sequentially formed on the first insulating layer(210) having a lower metal interconnection(212). The first photoresist layer pattern for forming a contact hole is formed on the third insulating layer. The third and second insulating layers are etched to expose the lower metal interconnection by using the first photoresist layer pattern as a mask, and the contact hole is formed. The first photoresist layer pattern is removed. The contact hole is filled with the second photoresist layer(224). The third photoresist layer pattern(226) for forming an upper interconnection is formed on the third insulating layer and the second photoresist layer. The third insulating layer and the second photoresist layer are etched to expose the second insulating layer by using the third photoresist layer pattern as a mask. The second and third photoresist layer are eliminated.

Abstract translation: 目的：提供一种用于制造双镶嵌结构的方法，通过形成用于形成上互连的开口，并且通过消除光致抗蚀剂层来防止接触孔的边缘被损坏，通过用光致抗蚀剂层填充接触孔 。 构成：第二和第三绝缘层（214,216）依次形成在具有较低金属互连（212）的第一绝缘层（210）上。 用于形成接触孔的第一光致抗蚀剂图案形成在第三绝缘层上。 通过使用第一光致抗蚀剂层图案作为掩模来蚀刻第三绝缘层和第二绝缘层以暴露下金属互连，并且形成接触孔。 去除第一光致抗蚀剂层图案。 接触孔填充有第二光致抗蚀剂层（224）。 用于形成上互连的第三光致抗蚀剂层图案（226）形成在第三绝缘层和第二光致抗蚀剂层上。 通过使用第三光致抗蚀剂层图案作为掩模，蚀刻第三绝缘层和第二光致抗蚀剂层以暴露第二绝缘层。 消除第二和第三光致抗蚀剂层。

公开(公告)号：KR1020000014553A

公开(公告)日：2000-03-15

申请号：KR1019980034037

申请日：1998-08-21

Applicant: 삼성전자주식회사

Inventor： 양희홍 ,  이대엽

IPC: H01L21/32

Abstract: PURPOSE: The method can form a wire area and a contact hole simultaneously using one mask, and the mask can form two pattern of different depth simultaneously. CONSTITUTION: The method comprises the steps of: forming a first insulation layer(102), a first etch stop layer(104), a second insulation layer(106) and a second etch stop layer(108) in sequence on a semiconductor substrate(100); forming a photoresist film pattern(110) on top of the second etch stop layer using a mask formed to have different transmittance in an area where a wire is formed and in an area where a contact hole is formed; removing the photoresist film pattern, after blanket etching; and forming a wire area(118) and a contact hole(120) simultaneously by etching the first and second insulation layer using the first and second etch stop layer as an etch mask. The method can prevent the misalign between the wire area and the contact hole and can simplify the process by reducing one photolithography.

Abstract translation: 目的：该方法可以使用一个掩模同时形成导线区域和接触孔，并且掩模可以同时形成两种不同深度的图案。 构成：该方法包括以下步骤：依次在半导体衬底上形成第一绝缘层（102），第一蚀刻停止层（104），第二绝缘层（106）和第二蚀刻停止层（108） 100）; 在所述第二蚀刻停止层的顶部上形成光致抗蚀剂图案（110），所述掩模形成为在形成所述导线的区域中具有不同的透射率，并且在形成有接触孔的区域中形成; 去除光刻胶膜图案; 以及使用第一和第二蚀刻停止层作为蚀刻掩模，通过蚀刻第一和第二绝缘层同时形成导线区域（118）和接触孔（120）。 该方法可以防止导线区域和接触孔之间的不对准，并且可以通过减少一个光刻来简化工艺。