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公开(公告)号：KR1020140131207A
公开(公告)日：2014-11-12
申请号：KR1020130050264
申请日：2013-05-03
Applicant: 삼성전자주식회사
IPC: G11C29/00
CPC classification number: G11C29/787 , G11C17/18 , G11C29/808
Abstract: 퓨즈 어레이에 페일 어드레스가 일단 프로그램된 후, 또 다른 페일 어드레스가 추가로 발생한 경우에, 이전 리페어 정보에 의존함이 없이도 미사용 퓨즈들을 검색하고 프로그램하는 반도체 메모리 장치가 개시된다. 그러한 반도메 메모리 장치는, 메모리 셀 리페어를 위한 페일 어드레스가 프로그램되도록 하기 위해 복수의 퓨즈들을 가지는 퓨즈 어레이와, 퓨즈 어레이 내에서 유휴 퓨즈들을 검색하고 추가로 발생된 또 다른 페일 어드레스를 프로그램하는 퓨즈 프로그래밍 회로를 포함한다.
Abstract translation: 公开了一种半导体存储器件，其对熔丝阵列中的故障地址进行编程，并且当产生另一个故障地址时，检索未使用的保险丝，而不依赖于以前的修复信息进行编程。 半导体存储器件包括：具有多个保险丝的熔丝阵列，用于编程用于存储器单元修复的故障地址; 以及熔丝编程电路，其检索熔丝阵列中的空闲熔丝并编程另外产生的另一失效地址。
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公开(公告)号：KR1020140106284A
公开(公告)日：2014-09-03
申请号：KR1020130020640
申请日：2013-02-26
Applicant: 삼성전자주식회사
IPC: G11C29/04
CPC classification number: G11C29/787 , G11C17/16 , G11C17/18 , G11C29/808 , G11C2229/763
Abstract: A memory device is provided. The memory device comprises an anti-fuse, a redundancy cell array, an anti-fuse setup unit, and a control unit. The anti-fuse authorizes a test data signal to a memory cell array to decide whether the memory cell is defective and programs the defective memory cell through an address corresponding to the proved defective memory cell. The redundancy cell array includes a first redundancy cell which replaces the defective memory cell. The anti-fuse setup unit stores the address of the first redundancy cell. The control unit senses the anti-fuse, the anti-fuse setup unit, and the redundancy cell array.
Abstract translation: 提供存储器件。 存储器件包括反熔丝，冗余单元阵列，反熔丝设置单元和控制单元。 反熔断器将测试数据信号授权给存储器单元阵列以决定存储器单元是否有缺陷，并通过与所证明的有缺陷的存储器单元相对应的地址对缺陷存储器单元进行编程。 冗余单元阵列包括替换缺陷存储单元的第一冗余单元。 反熔丝设置单元存储第一冗余单元的地址。 控制单元感测反熔丝，反熔丝设置单元和冗余单元阵列。
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公开(公告)号：KR1020100058892A
公开(公告)日：2010-06-04
申请号：KR1020080117474
申请日：2008-11-25
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242
CPC classification number: G11C11/4091 , G11C7/065 , G11C7/12 , G11C11/4094 , G11C2207/005
Abstract: PURPOSE: A semiconductor memory device with only bit line on memory cell is provided to only require one N-type sensing amplifier for sensing a bit line by accepting data stored in a memory cell only through a bit line. CONSTITUTION: A first memory cell is formed within a first memory cell array block. A second memory cell is formed within a second memory cell array block. A bit line(BL) is connected to a first memory cell(MC1) through a first separation transistor. The bit line is connected to a second memory cell(MC2) through a second isolating transistor.
Abstract translation: 目的：仅存储器单元上的位线的半导体存储器件仅需要一个N型检测放大器，用于仅通过位线接受存储在存储器单元中的数据来感测位线。 构成：在第一存储单元阵列块内形成第一存储单元。 在第二存储单元阵列块内形成第二存储单元。 位线（BL）通过第一分离晶体管连接到第一存储单元（MC1）。 位线通过第二隔离晶体管连接到第二存储单元（MC2）。
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Patent Agency Ranking
公开(公告)号：KR1020140046854A
公开(公告)日：2014-04-21
申请号：KR1020120113033
申请日：2012-10-11
Applicant: 삼성전자주식회사
IPC: G11C17/00
CPC classification number: G11C17/08 , G11C16/04 , G11C16/0483 , G11C17/16 , G11C17/18 , G11C29/785
Abstract: Disclosed is a semiconductor memory device including an OTP cell array, a convergence unit, and a sense amplifier. The semiconductor memory device according to an embodiment of the present invention can include an OTP cell array including OTP cells and bit-lines. The OTP cell array outputs signals corresponding to the bit-data stored in the OTP cells through the bit-lines. The convergence unit transmits signals of one or more bit-lines among the multiple bit-lines to the sense amplifier. The convergence unit, according to the embodiments of the present invention, can be controlled by addresses and include coupling nodes connecting multiple bit-lines.
Abstract translation: 公开了包括OTP单元阵列，会聚单元和读出放大器的半导体存储器件。 根据本发明的实施例的半导体存储器件可以包括包括OTP单元和位线的OTP单元阵列。 OTP单元阵列通过位线输出与存储在OTP单元中的位数据相对应的信号。 会聚单元将多个位线中的一个或多个位线的信号发送到读出放大器。 根据本发明的实施例的收敛单元可以由地址控制，并且包括连接多个位线的耦合节点。
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公开(公告)号：KR1020130113679A
公开(公告)日：2013-10-16
申请号：KR1020120036055
申请日：2012-04-06
Applicant: 삼성전자주식회사
IPC: G11C17/18
CPC classification number: G11C17/16 , G11C7/20 , G11C17/18 , G11C29/789 , G11C2029/4402
Abstract: PURPOSE: A method of reading data stored in a fuse device and devices using the same improve the performance of a memory device including a fuse device by reading data in a predetermined order. CONSTITUTION: Trimming data associated with the trimming of a voltage or a current required for operation of a memory device is read from a fuse device (S20). Mode register set (MRS) data associated with the setting of a mode register included in the memory device is read from the fuse device (S22). Defective cell address data associated with defective cells included in a memory cell array of the memory device is read from the fuse device (S24). [Reference numerals] (S20) Trimming data is read from an anti fuse device; (S22) MRS data is read from the anti fuse device; (S24) Defective cell data is read from the anti fuse device
Abstract translation: 目的：读取存储在保险丝装置中的数据的方法和使用其的装置，通过以预定顺序读取数据来改善包括熔丝装置的存储装置的性能。 构成：从保险丝装置读取与修整存储器件操作所需的电压或电流相关的修整数据（S20）。 从保险丝装置读出与存储装置中包含的模式寄存器的设定有关的模式寄存器组（MRS）数据（S22）。 从保险丝装置读取与存储装置的存储单元阵列中包含的缺陷单元有关的不良单元地址数据（S24）。 （附图标记）（S20）从反熔丝器件读取修整数据; （S22）从反熔丝器件读取MRS数据; （S24）从反熔丝器件读取不良的电池数据
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公开(公告)号：KR1020130111781A
公开(公告)日：2013-10-11
申请号：KR1020120033936
申请日：2012-04-02
Applicant: 삼성전자주식회사
CPC classification number: G11C17/18 , G11C7/14 , G11C17/16 , G11C29/789
Abstract: PURPOSE: A fuse data reading circuit with multiple reading modes minimizes reading errors of fuse data in a section that the reading operation environment is unstable by reading the fuse data in multiple reading modes. CONSTITUTION: A fuse array (140) includes multiple fuse cells storing fuse data. A sensing unit (150) senses the fuse data stored in the fuse cells of the fuse array. A controller (110) controls the operation of reading the fuse data stored in the fuse cells. The controller differently sets sensing conditions to sense the fuse data according to operation sections in the fuse data reading operation and reads the fuse data.
Abstract translation: 目的：具有多种读取模式的保险丝数据读取电路通过在多种读取模式下读取保险丝数据来最大限度地减少读取操作环境不稳定的部分中的熔丝数据的读取错误。 构成：熔丝阵列（140）包括存储熔丝数据的多个熔丝单元。 感测单元（150）感测存储在熔丝阵列的熔丝单元中的熔丝数据。 控制器（110）控制读取存储在熔丝单元中的熔丝数据的操作。 控制器不同地设置感测条件以根据熔丝数据读取操作中的操作部分感测熔丝数据，并读取熔丝数据。
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公开(公告)号：KR1020140065218A
公开(公告)日：2014-05-29
申请号：KR1020120132477
申请日：2012-11-21
Applicant: 삼성전자주식회사
IPC: G11C29/00
CPC classification number: G11C29/808 , G11C29/76 , G11C29/787 , G11C2229/763
Abstract: The present invention relates to a semiconductor memory device to perform a post package repair using an anti-fuse circuit and a post package repair method thereof. According to the present invention, the post package repair method of the semiconductor memory device comprises the steps of: receiving a post package repair command; comparing an available number of redundancy bits (hereinafter, a number of available bits) with a number of faulty bits to determine the feasibility of the post package repair command in response to the post package repair command; and selectively replacing a defective cell with a redundancy memory cell based on the comparison result.
Abstract translation: 本发明涉及使用反熔丝电路进行后封装修复的半导体存储器件及其后封装修复方法。 根据本发明，半导体存储器件的后封装修复方法包括以下步骤：接收后封装修复命令; 将可用数量的冗余比特（以下称为可用比特数）与多个错误比特进行比较，以确定响应于后包修复命令的后包修复命令的可行性; 并且基于比较结果用冗余存储单元选择性地替换有缺陷的单元。
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