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公开(公告)号：KR1020130043835A
公开(公告)日：2013-05-02
申请号：KR1020110107968
申请日：2011-10-21
Applicant: 삼성전자주식회사
Inventor： 유철준
CPC classification number: H01L2224/48091 , H01L2224/73265 , H01L2924/181 , H01L33/58 , H01L33/62 , H01L2933/0016 , H01L2933/0058 , H01L2933/0066 , H01L2924/00014 , H01L2924/00012
Abstract: PURPOSE: A light emitting device package, a method for manufacturing the same, and an illuminating device having the same are provided to form an electrode pattern on the upper surface of a ceramic substrate, to omit a separate circuit substrate for electrically connecting the ceramic substrate, and to reduce manufacturing costs. CONSTITUTION: Electrode patterns(110,120) are formed on the upper surface of a substrate(100). A light emitting device(200) is connected to the electrode patterns. A lens unit(300) covers the electrode patterns and the light emitting device. The lens unit includes a flange part(310) for protecting the electrode patterns and a lens unit(320) for encapsulating the light emitting device. Opening parts(330) for exposing parts of the electrode patterns are formed in the lens unit.
Abstract translation: 目的：提供一种发光器件封装，其制造方法和具有该发光器件封装的照明装置，以在陶瓷衬底的上表面上形成电极图案，省略用于电连接陶瓷衬底的单独的电路衬底 ，并降低制造成本。 构成：电极图案（110,120）形成在基板（100）的上表面上。 发光器件（200）连接到电极图案。 透镜单元（300）覆盖电极图案和发光器件。 透镜单元包括用于保护电极图案的凸缘部分（310）和用于封装发光器件的透镜单元（320）。 在透镜单元中形成用于暴露部分电极图案的开口部分（330）。
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公开(公告)号：KR1020130022606A
公开(公告)日：2013-03-07
申请号：KR1020110085301
申请日：2011-08-25
Applicant: 삼성전자주식회사
Inventor： 유철준
CPC classification number: F21V17/12 , F21K9/232 , F21K9/61 , F21V3/00 , F21V5/041 , F21V17/16 , F21Y2115/10
Abstract: PURPOSE: A lighting device is provided to send sides and the rear side as well as the front side, thereby significantly improved light distribution characteristics. CONSTITUTION: A light source(100) is mounted on a substrate(120) and includes a light emitting display(110) built in the substrate to be electrically connected with a circuit wiring. A light guide part(200) is mounted on the substrate in order to cover the light emitting display. The light guide part comprises a guide portion(210) guiding the light of the light emitting display and a lens unit(220) emitting the light guided through the guide portion. A main body unit(300) emits heat generated in the light source to the outside. The main body part comprises a power supply device(310) supplying power source to the light source and an external terminal(320) connected with external power. A cover unit(400) is mounted on the upper part of the main body unit to protectively cover the light source and the light guide part.
Abstract translation: 目的：提供照明装置以发送侧面和后侧以及前侧，从而显着改善光分布特性。 构成：将光源（100）安装在基板（120）上，并且包括内置在基板中以与电路布线电连接的发光显示器（110）。 导光部（200）安装在基板上以覆盖发光显示器。 导光部分包括引导发光显示器的光的引导部分（210）和发射通过引导部分引导的光的透镜单元（220）。 主体单元（300）将在光源中产生的热量发射到外部。 主体部分包括向光源提供电源的电源装置（310）和与外部电源连接的外部端子（320）。 盖单元（400）安装在主体单元的上部，以保护地覆盖光源和导光部。
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公开(公告)号：KR1020120083714A
公开(公告)日：2012-07-26
申请号：KR1020110005010
申请日：2011-01-18
Applicant: 삼성전자주식회사
IPC: H01L33/50
CPC classification number: H01L2224/16
Abstract: PURPOSE: A method of coating phosphor layer on the LED chip is provided to increase uniformity and productivity by coating with phosphor after forming constant intervals between light emitting chips in advance. CONSTITUTION: A plurality of light emitting chips(150) are arranged on an extensible film(110). Intervals between the plurality of light emitting chips transferred onto a thermal resistant film(120) are formed by expanding the extensible film. A phosphor material is coated on the top and side of the plurality of light emitting chips. The extensible film is composed of a polyolefin material.
Abstract translation: 目的：提供一种在LED芯片上涂布荧光体层的方法，以便在预先在发光芯片之间形成恒定间隔之后，通过用磷光体涂覆来提高均匀性和生产率。 构成：多个发光芯片（150）布置在可延伸膜（110）上。 转印到耐热薄膜（120）上的多个发光芯片之间的间隔通过扩展可伸长薄膜而形成。 磷光体材料涂覆在多个发光芯片的顶部和侧面上。 可延伸膜由聚烯烃材料组成。
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公开(公告)号：KR1020090132000A
公开(公告)日：2009-12-30
申请号：KR1020080058044
申请日：2008-06-19
Applicant: 삼성전자주식회사
Inventor： 유철준
CPC classification number: H01L2224/10
Abstract: PURPOSE: A wafer level stack package, a manufacturing method thereof, and a semiconductor manufacturing apparatus are provided to prevent a contact failure by forming a bump and a through electrode inside a via through high pressure injection at the same time. CONSTITUTION: A wafer level stack package includes a plurality of semiconductor packages(110~140). The semiconductor packages are laminated by adhesives. Each semiconductor package includes a wafer(111) and a contact pad(113). The contact pad is arranged to one surface of the wafer. A via penetrates the contact pad and the wafer. A through electrode(160) is formed inside the via. A contact terminal(170) is formed to one of the semiconductor packages.
Abstract translation: 目的：提供晶片级堆叠封装，其制造方法和半导体制造装置，以通过同时通过高压注入在通孔内形成凸块和通孔来防止接触故障。 构成：晶片级堆叠封装包括多个半导体封装（110〜140）。 半导体封装通过粘合剂层压。 每个半导体封装包括晶片（111）和接触焊盘（113）。 接触垫布置在晶片的一个表面上。 A通孔穿透接触垫和晶片。 在通孔内部形成贯通电极（160）。 接触端子（170）形成于半导体封装之一。
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公开(公告)号：KR100836769B1
公开(公告)日：2008-06-10
申请号：KR1020070059597
申请日：2007-06-18
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L2224/13 , H01L2224/73104
Abstract: A semiconductor chip package and a manufacturing method thereof are provided to improve solder bonding reliability by forming a molding layer, which covers an active surface of a semiconductor chip and has a meniscus concave surface. A semiconductor chip(110) includes an active surface having bonding pads thereon, a rear surface, and a side surface. The rear surface is opposed to the active surface. Solder balls(112) for bumps are provided on the bonding pads of the semiconductor chip. The solder balls electrically couple the semiconductor chip with an external circuit. A molding layer(120c) covers the active surface of the semiconductor chip and exposes a portion of the solder balls. The molding layer has a meniscus concave surface, which includes an edge adjoined with the solder balls between the adjacent solder balls. The solder balls have a cross-section, which is parallel to the active surface and has a maximum diameter.
Abstract translation: 提供半导体芯片封装及其制造方法，以通过形成覆盖半导体芯片的有源表面并具有弯月面凹面的成型层来提高焊接接合可靠性。 半导体芯片（110）包括其上具有接合焊盘的活性表面，后表面和侧表面。 后表面与活性表面相对。 用于凸块的焊球（112）设置在半导体芯片的接合焊盘上。 焊球将半导体芯片与外部电路电耦合。 模制层（120c）覆盖半导体芯片的有源表面并暴露一部分焊球。 成型层具有弯月面凹面，其包括与相邻焊球之间的焊球相邻的边缘。 焊球具有平行于活性表面并具有最大直径的横截面。
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Patent Agency Ranking
公开(公告)号：KR1020080046825A
公开(公告)日：2008-05-28
申请号：KR1020060116326
申请日：2006-11-23
Applicant: 삼성전자주식회사
IPC: H01L21/324 , H01L21/477
CPC classification number: H01L21/67092 , H01L21/268 , H01L21/78
Abstract: An apparatus for sawing a semiconductor wafer is provided to prevent a semiconductor chip from being contaminated and being reduced in strength by absorbing the fragments generated in sawing a semiconductor wafer by a fragments absorption unit. A laser light emitting unit(130) irradiates a laser beam to the surface of a wafer. A driving unit transfers the laser light emitting unit. A fragment absorption unit(200) is installed in the driving unit, transferring together with the laser light emitting unit, having a body surrounding the laser beam irradiated from the laser light emitting unit. The body can include a cylindrical inner wall(210) surrounding the laser beam and a cylindrical outer wall(220) surrounding the inner wall wherein a space between the inner and outer walls is connected to a space surrounded by the inner wall through a plurality of absorption holes(230) penetrating the lower part of the inner wall.
Abstract translation: 提供锯切半导体晶片的装置，以防止半导体芯片受到污染并通过吸收通过碎片吸收单元在锯切半导体晶片中产生的碎片而降低强度。 激光发射单元（130）将激光束照射到晶片的表面。 驱动单元传送激光发射单元。 碎片吸收单元（200）安装在驱动单元中，与激光发射单元一起转移，其具有围绕从激光发射单元照射的激光束的主体。 主体可以包括围绕激光束的圆柱形内壁（210）和围绕内壁的圆柱形外壁（220），其中内壁和外壁之间的空间通过多个 吸收孔（230）穿透内壁的下部。
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公开(公告)号：KR1020080029197A
公开(公告)日：2008-04-03
申请号：KR1020060094944
申请日：2006-09-28
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
Abstract: A semiconductor device package and a method for manufacturing the same are provided to secure the reliability of a semiconductor device and to reduce a manufacturing cost. A semiconductor substrate having a metal line layer(116) is provided. A land layer(118) having an opening is formed to expose the metal wiring layer. A singulation process is performed to divide the semiconductor chip in chip units. A surface mounting process is performed to connect electrically the metal line layer and the system board to each other. The metal wiring layer includes copper. The opening is extended gradually from a center of a chip to an edge of the chip. The metal line layer includes copper. The metal line layer is formed by re-wiring a bonding pad(112) included in the semiconductor substrate.
Abstract translation: 提供半导体器件封装及其制造方法以确保半导体器件的可靠性并降低制造成本。 提供具有金属线层（116）的半导体衬底。 形成具有开口的接地层（118），露出金属布线层。 执行单片化处理以将芯片单元划分成半导体芯片。 执行表面安装处理以将金属线层和系统板电连接到彼此。 金属布线层包括铜。 开口从芯片的中心逐渐延伸到芯片的边缘。 金属线层包括铜。 通过重新布线包括在半导体衬底中的接合焊盘（112）来形成金属线层。
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公开(公告)号：KR100803679B1
公开(公告)日：2008-02-20
申请号：KR1020060112577
申请日：2006-11-15
Applicant: 삼성전자주식회사
IPC: H01L23/28
CPC classification number: B29C43/183 , B29C33/68 , B29C43/146 , B29C2043/3411 , B29C2043/3605 , B29K2105/251 , B29L2031/772 , H05K3/0014
Abstract: A method for manufacturing a molding structure and a method and an apparatus for molding a substrate are provided to shorten a time required for a molding process by forming the molding structure used in molding of the substrate prior to a substrate molding process. A first release film is attached to an upper portion of a lower mold(S110), and then powder of an epoxy molding compound is applied on the first release film(S120). A second release film is attached to a bottom surface of an upper mold opposite to the lower mold(S130), and then the power is pressed by using the upper and lower molds to form a flat EMC(Epoxy Molding Compound)(S140). The upper and lower molds are detached with the first release film attached to the flat EMC, thereby forming a molding structure composed of the flat EMC and the first release film(S150).
Abstract translation: 提供了一种用于制造模制结构的方法以及用于模制基底的方法和装置，以便在基底模制过程之前形成用于模制基底的模制结构来缩短模制过程所需的时间。 将第一剥离膜附着到下模的上部（S110），然后将环氧模塑料的粉末施加在第一剥离膜上（S120）。 第二剥离膜附着在与下模相对的上模的底面上（S130），然后通过上模和下模压制动力，形成扁平的EMC（环氧模塑料）（S140）。 上模和下模与第一离型膜分离，连接到扁平EMC，从而形成由扁平EMC和第一脱模膜构成的模制结构（S150）。
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公开(公告)号：KR100783102B1
公开(公告)日：2007-12-07
申请号：KR1020050003751
申请日：2005-01-14
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H05K3/3436 , H01L23/3128 , H01L24/10 , H01L24/13 , H01L24/48 , H01L2224/13 , H01L2224/13099 , H01L2224/48091 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H05K3/3452 , H05K3/3484 , H05K2201/10977 , H05K2203/0568 , Y02P70/613 , H01L2924/00 , H01L2224/0401 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: 본 발명은 종래의 솔더 볼 대신에 솔더 기둥을 이용한 반도체 패키지의 기판 접합 구조 및 방법에 관한 것이다. 반도체 패키지와 패키지 실장 기판에서 서로 마주보는 면에 각각 형성된 절연 보호막은 종래에 비하여 두껍게 형성되며, 솔더 기둥은 절연 보호막의 개구부를 통하여 배선층에 접합된다. 이 때, 양쪽 절연 보호막의 두께 합은 솔더 기둥의 높이의 약 20% 내지 약 100%이며, 바람직하게는 약 80%이다. 따라서 절연 보호막이 솔더 기둥의 주위를 감싸게 되어 접합 신뢰성을 향상시킬 수 있다.
볼 그리드 어레이 패키지(BGA package), 패키지 실장 기판, 솔더 볼(solder ball), 솔더 기둥(solder column), 포토 솔더 레지스트(PSR)-
公开(公告)号：KR100640580B1
公开(公告)日：2006-10-31
申请号：KR1020040041855
申请日：2004-06-08
Applicant: 삼성전자주식회사
Inventor： 유철준
IPC: H01L23/04
CPC classification number: H01L21/561 , H01L21/565 , H01L23/13 , H01L23/3114 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: 본 발명의 반도체 패키지는 PCB 기판 상에 표면을 하향하여 실장되는 반도체 칩과, 상기 반도체 칩과 상기 PCB 기판을 전기적으로 연결하는 본딩 와이어와, 상기 반도체 칩의 배면, 상기 PCB 기판의 측면 및 상기 PCB 기판의 하면 가장 자리 부분에 형성되어 상기 PCB 기판의 측면을 충분히 감싸 밀봉하는 봉지재와, 상기 PCB 기판의 하면에 부착되는 솔더볼을 포함하여 이루어진다. 이에 따라, 본 발명의 반도체 패키지는 PCB 기판의 측면이 노출되지 않아 봉지재와 PCB 기판이 분리되는 박리 현상을 방지할 수 있고, 반도체 칩으로 습기가 침투하는 흡습 경로를 차단할 수 있다.
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